From patchwork Wed Mar 14 07:56:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 131561 Delivered-To: patch@linaro.org Received: by 10.46.84.17 with SMTP id i17csp548342ljb; Wed, 14 Mar 2018 00:58:59 -0700 (PDT) X-Google-Smtp-Source: AG47ELudAhNGxW8ZPyeXbkpoihAzAyhEUHJtik/Rdlg2yKCj655nVwfH2EYiglZkuy9HwwdvxJQc X-Received: by 10.223.185.73 with SMTP id b9mr2962765wrg.229.1521014339393; Wed, 14 Mar 2018 00:58:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521014339; cv=none; d=google.com; s=arc-20160816; b=zLQxBE3iOH+AvP/jl94I+Abebrmf3zLxrSf8ZG8ECLcoGU4Bgr5by/qkDz5C+FcwAa fsMYl+bgBxpZNXQfGK/9VSAfJB0R9GGGB8C2wkk/xrPo9X0h2PrXq8SToU2LK5xV59dj aHtpF4xQ4LiVUGSDR6AF4AAlMSLh7J9mogjIAAt+rcKlJvVkzLS9exgNDQW9QY3P8ygc SpE/YzEiN8ThpxN0dEop7u8p/ELiMVM4U60/azRnfIBkzSl6KVYl/AW7ZmjFuBWRVKeG FXjUOGcKgkpb8pFGx0vpVqo2iOrenXZGL9JUh7uF/jgsm8EHwklOGgncZovi6pBxe+VP wjaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:spamdiagnosticmetadata :spamdiagnosticoutput:mime-version:references:in-reply-to:message-id :date:cc:to:from:dkim-signature:arc-authentication-results; bh=xJfAVFm0tthY3qHCJROHhrAx32uWGu+lp3fqtVR+2lk=; b=a5G9/Yl3Y1H7znj6m1+3C5k4OjvzNDGwV3a4e/7axbsKoD1P8RuybRS5lJ4LBtmtnc JDhMtvaya4Kzn/GvcW4ILWbTzuFfQ6vZ++U827rLryATU40vzk2wimJh+TPFdEc1wWGb xOD33SLgjjt5JV/auKh4VHmchrtDZ84gNEJEomKxIVGq+Jz4oEAsIdarnbsildaEmHjR 5gfcvMfD4Ky4Hg1jlVg+cLBwD6CmIGqRS0Dc7ez9e3YccnQki2E/wGUMEXejzEJdOVkc nb5DX2Tzyu6J25RGaEdyDShE6r+0UQu8AIupuykwaXN2khkVflZ5ePJgNQUWvYtA1vWu 31MQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=NQrr9mGW; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id r8si496256wmb.115.2018.03.14.00.58.59; Wed, 14 Mar 2018 00:58:59 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; dkim=fail header.i=@nxp.com header.s=selector1 header.b=NQrr9mGW; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 63014A495; Wed, 14 Mar 2018 08:58:09 +0100 (CET) Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40048.outbound.protection.outlook.com [40.107.4.48]) by dpdk.org (Postfix) with ESMTP id 3EC447CFD for ; Wed, 14 Mar 2018 08:58:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=xJfAVFm0tthY3qHCJROHhrAx32uWGu+lp3fqtVR+2lk=; b=NQrr9mGWf3J3DsE42LWj9vRteFQXf6oS3/iJ889K4TXIkc6RpJkAd1C4e7ly1/wrPV7o6/bmQ4Rmla8tLa7i44c871NkvuaSZNNKg8hyFrBIgGfz3t7sQPz0lAmSykx/UvVQfW42rrxJx3UXe4CdYCyI5cMKMmFBRqgYDQVnh8E= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=hemant.agrawal@nxp.com; Received: from bf-netperf1.ap.freescale.net (14.142.187.166) by AM2PR04MB0754.eurprd04.prod.outlook.com (2a01:111:e400:8411::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.548.13; Wed, 14 Mar 2018 07:58:03 +0000 From: Hemant Agrawal To: dev@dpdk.org, bruce.richardson@intel.com Cc: thomas@monjalon.net Date: Wed, 14 Mar 2018 13:26:00 +0530 Message-Id: <1521014166-3201-5-git-send-email-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521014166-3201-1-git-send-email-hemant.agrawal@nxp.com> References: <1519889597-5805-1-git-send-email-hemant.agrawal@nxp.com> <1521014166-3201-1-git-send-email-hemant.agrawal@nxp.com> MIME-Version: 1.0 X-Originating-IP: [14.142.187.166] X-ClientProxiedBy: BM1PR0101CA0008.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:18::18) To AM2PR04MB0754.eurprd04.prod.outlook.com (2a01:111:e400:8411::14) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7fe90903-7013-4e40-e321-08d5898150b4 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(4534165)(7168020)(4627221)(201703031133081)(201702281549075)(2017052603328)(7153060)(7193020); SRVR:AM2PR04MB0754; X-Microsoft-Exchange-Diagnostics: 1; AM2PR04MB0754; 3:KQ+UW/yUr6EAlJA0apOEzA3tBRErf1yYcJI37G4XKSdkMO4bby1M1Fb3JYEYibF6oYuvwQhXxqeP4sH8hf4wVTqK0gQlb8p1PAFnmB/0Sf1nW72Kdyl6jf0qwpD/ELr/VS5G+mhbwuAe0E44mNcHu2EybshUUwyx2+DT3LZnXxbvWk+zgrfvC8gUf3kCoeSIL68L4e+X+uG4ls04OkBElxQ3OnThh+ZAC82GcCwZvu7NK4tRehIfjapfdmxUfzMk; 25:TO0HnK1/k8jIZzQO1Hu+A8hgsz+5/qvegF9sS5qGGuDrqojC5HC1vlYaECZzusdmL1cTAGItpOFHZi6CQFDEBNcskfd69+5W+OvM72N646p6UtcznP6lZFEGsygL64+ltpcWabWY9n4VKtkyoO02fqlYnPh+0tyTulCqWQNzdcTK+ytOYY7zNhCO3JdIbglHbZ5BbRC9SOWRZn4mbqrmzprDK/petffcvYbPB6HJSajd6glWZhNQYniUHro3qiWJxmnbzByy4rjk6HgR6YRmn6QLpvd8mvBH9paD3kD4hv5TZNue/R6B1vLJnsBOHE6KoB4pLItTSu3PouKZNuaSjQ==; 31:eK7prLpk0uSAZRT3mRTh4fxzKdy0L8jCZG5bhKoLNWbxDE5R4OIXLXcRNyW/fDQEVKCgl96s5K6lFxIyeYRkUlMb+UXpknTWTUaF6M0UVk+8YaJRJ4XnK2zZcDpBpK+TNoZCbdYT6zLlLXgipeSm+dGbaxf5AIiIJKG84BRm4mjYdBsURZZMyGRd1FYcUUL132se0fXS9QYT3ZOFlkJhKMylC9VMalPkOvV+uuMiLFk= X-MS-TrafficTypeDiagnostic: AM2PR04MB0754: X-Microsoft-Exchange-Diagnostics: 1; AM2PR04MB0754; 20:FHjP65vt64L3iYU83SzCoH8yoQgN9LxZp32gTN9KfIPC3GTTvojamXLGLE0ekJRZX65xiVTEMdMY2qbZ1BxMuvnEoKJ96S244cKZ16BAKgKazwF5/xaj7dA6IO+VeB6cIi6SDAUzCnjLk1w//8KfVCbVF9smLOW5+6QAvzYoL1MOelveSk7D63YCYSK5EHrD9b+q73vZar/WLEFYgER19ol1burWPWcSnrWgM4dGiw+eM+21cZJGb6dof9rz8DqX/mcWFsOhovD9hsKQ+ZSs4cYn6ZtU2cwfjHahFXREKpWsmgWS32y51RrLh1ZEI2Wl/ArO55HggGrV9C2ODivJaoabkxHrPSWEnIfqHs5x4FdtVoijrQJAOjLE69SMTPGLY9y/sD9EqOPkzrZsP9E1KpaC1bAgD6gL49rz0yMK6lv5v8v9QGx2nQ1UZlswGf21hjWGLRG51Ug1B7SM5lClvD77XKv6sNz8/jvYUQWUWTRD2wYM2qoDwscdI1DmZeTW; 4:0pBRoplJg7YLd1a+e62oJjeq4RA8Hp0Qp9JO8tBFaF0h6em1tRxvyO324KtPsAJQJ3eFvCwEm1mdBwvM4mNqxWyEaObaeFyex8cT9i8Rn4LgE89HGmzXZK3IQtN+NYjUXbNgcw8r5LzTUrL9Lr9I+WbYk+5Wo/oTwgnFXDQmfUCN9V2SE+pWASOyKvIQgZRwlHBDoERVxAZ1ZpJre17aBgmmI/hn4dCny/OhftFlvMz/JxUIRfcGoVSfEIc2YUwTXv2hcYIp/rKSpuVBr9puAwwbccPScZ25+hFPLkb7I5BP+jSIWHTTXobJsaKjDWuxM7Y+thgh8MLSqGj6VWjO7jbIdTwICCoiC4xchp/gKGk= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(275809806118684); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3231221)(944501244)(52105095)(93006095)(93001095)(3002001)(10201501046)(6055026)(6041310)(20161123558120)(20161123562045)(20161123564045)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(6072148)(201708071742011); SRVR:AM2PR04MB0754; BCL:0; PCL:0; RULEID:; SRVR:AM2PR04MB0754; X-Forefront-PRVS: 0611A21987 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(376002)(39860400002)(346002)(39380400002)(396003)(366004)(199004)(189003)(316002)(4326008)(16526019)(575784001)(47776003)(6506007)(66066001)(186003)(52116002)(86362001)(386003)(55236004)(59450400001)(48376002)(2906002)(97736004)(53946003)(68736007)(26005)(5660300001)(25786009)(105586002)(76176011)(51416003)(6512007)(50466002)(5009440100003)(36756003)(16586007)(81166006)(6486002)(8936002)(106356001)(305945005)(7736002)(50226002)(6116002)(53936002)(81156014)(8676002)(5890100001)(2950100002)(3846002)(478600001)(110426004); DIR:OUT; SFP:1101; SCL:1; SRVR:AM2PR04MB0754; H:bf-netperf1.ap.freescale.net; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM2PR04MB0754; 23:tuEdXnY7ZfrISnTjwiAg/1Hh7Hm7YsL1jmeEaR/cm?= CQV2mc1BucTJyZAKYtql5gknPEevGCvzWOqyuxQ9NuqHaM44vSyUL48FgUtivR6dRGy7bxwYAphmxdmKRUNfg80gMZbLN+POnhhpFmUf/BGcHbyJzQWJikDVHqPR0V50Iprx2OjHx2+9INUs5hYNKH8i6YTtegxm3TG87P19m/n39z4M9zVqTtpqsmpPlJYAg1x7PEJnUiBUrIKfy9yNipOQ0yjqixyoKy3AVSEYdLz58ETCzm+t8lxIVtlQeLrMgCtrK2Qhf/q1gU/IO74J7SjVkyiDbdzPj+cRpi4K3Xwwo6dgt7JDlz+p+5eER/HyLLlB7lU0Iw63JCRUkAgtmb3rpLvj1BzOjqIPkdfK6FWNLtFCOFBPK+B/fJlB20br3Zg/zLLqNfqR0YnytPyUT+HGbSYASWQXn/NdEeah/znTB1jTsoTApnOTJY/7yj4TlPnNl8oqpEpVJG4I57iI3vLUkit5uhrtKwoU16/Lx5hNG74bMsikOf4rhUt4aQMXCw2/mh5ubi+IGw3EtTiddckDA4gRRUPSKZRQ50mSwmkXqYEVrtLONsXxQkpkmFhyVRTYkFelab6Sl+pa/OUJY/Rfw3JBVIpCwacn+RHLSXB1HJ9zlD6npg5Kb4PxYORhoIjPgeqKt+JDyXA9tp9/rBenEK/yzmZVPQ2BtHmA/JlUgW7aKUvSo4oVzGB4bHK2zEqg2hzL/IQiEbd0Rxew3pHpWVTohJFAeSs3pKV1CcV+1pxcJHnLYpqrsmcE8sRlKGwy5BM7yalm0hC4V+wZ/xYTM92H1Mm5l46E9itD+RHmJlUuqXdiylmqBku9NYfPfD+cPvuNFNOcgpUdf2QB/CLcscZfOfXlrU45jyl5nLNGz5onGHS00Za+XTo4TfrTKtsDrLwF0tw7EitthevwaYzCRhbPygSjsSfiAgdjsNJBqbGiHNspGI3A91qiZBmL1cqcZEL9m8nutF9dZycL7Yeju5kZQ6SLFovD8tKWvGN6j2+EwevkqGHjLBqgy3ULZ5M50fBbeJDYTcopZdzL8aRmVxfb0B8Poe+44q6rlu6Izc1XsLImOiIL9sYmjptmATsQsk67K0YU6sVxTLOiwaTLGBIvKjuQ+NJ8pHuqz/JHkKXrrfk4BS4ow9Td62/R/4+ydgm73ykMdq/EB3P0QksM5xK26QpoIu+9gQbcxHnCEnTEhnym514hZSybVcr1qQ= X-Microsoft-Antispam-Message-Info: eFavhgRnwdBo1cKZWCzvx29zHwEanfcfSdSP4/w5Ci+EErsD1lb9zIwrJvonFYK8IfHunia/yPulV+nAHhL6cYCUzSrSc/5stRIpu1VoYEOkyclh1bzvOrHzrYA5/aiMe1PtOWUThs0SgKGUVHWFYihGYoohP3l/CCO9UxApV3ql722GNgqbP47WMphtGOIO X-Microsoft-Exchange-Diagnostics: 1; AM2PR04MB0754; 6:GGEPS+8TnKlZudVjT1dNt/Ax5ZY2OGOFRYTivTykSuK7Re0DYqQULiut0AiGgjenzE/Ld583+bsL+kjEpzbzMUX0NPInhEtG/nh36gB/YHiNBkp+eEuv63N+JBvLk9LGIJ0hw2WJzfGwSrOOPagslqDj4ztXkqOjZGXD37zqH8RrBRjNazxDjSmEqOF2td6KUSJ1XIbr5sC1GB/ZAd4/0F9lLnp5XjqW8gqcEFTi+ZJDla9FYibvhEo/1i0IrWkk48yBnQVz9wcwSfWJwHwm1CWmNaCklEPVVjmQCBzCEK7xjsmAd825/vhzRNYLpIEjSCWF2t95VJcIwNFrVDGkwmXIT9pJkmdg61lKIBmUc4I=; 5:ER/u4CZcIvEhzwHH69/1EySbtPL0W2o7NoXmflfEOC7LbN+1ZT1INR2gO6eAR3qg1l+hXw4AsmnX5CiF54Lp2+J17whwus43owLcZi8cCTyPytaSuOwqSOjJhPKhG44bJl7xR9icoazv1yWeIQYbX74FXnALnnnK/3H2gIfkXjo=; 24:au4/TRo1z0e+tYORnnq/K7Rv6h8ES8j1K1PeZ2wVCw6P5HEvpYRBYO9rNUYqW19co5lRC4tKck+8t0ZsHQ8CDBlBCBFjcvcCDm1dY2EK7rw=; 7:IVDBxy6QstO4qTa0hXKjgoKt3/7uJrW4b0OzvupxVFL9xxzQNcp3RjLeBLukJpR9c43js2LdFraXfxiHOySA2PIXW+N11SzaUO5qkNkqZAJ/m7WS9B9/mZcVCz0Ti8NwB9FBIeq9f/YCOZr6TKgw2cza/E5PAbM6Hrsju5Dao2h//uudF2S9CwpNqhfMd6EfXqJzsGX5k+MyqAM7wr6TsDXa0Ebx2pFizDL3bdsi/Cz3m9ynDMv7J9gV0u0eeckI SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2018 07:58:03.2954 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fe90903-7013-4e40-e321-08d5898150b4 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM2PR04MB0754 Subject: [dpdk-dev] [PATCH v3 04/10] dpaa2: prepare for 32 bit compilation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch prepare the dpaa2 drivers for compilation on 32 bit machine. Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/fslmc_vfio.c | 10 +-- drivers/bus/fslmc/mc/fsl_mc_cmd.h | 2 +- drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 22 +++--- drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 37 +++++----- drivers/bus/fslmc/qbman/qbman_portal.c | 14 ++-- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 101 ++++++++++++++-------------- drivers/event/dpaa2/dpaa2_eventdev.c | 10 +-- drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 8 +-- drivers/net/dpaa2/Makefile | 1 - drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 2 +- drivers/net/dpaa2/dpaa2_ethdev.c | 6 +- drivers/net/dpaa2/dpaa2_rxtx.c | 63 +++++++++-------- 12 files changed, 137 insertions(+), 139 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c index 1241295..e840ad6 100644 --- a/drivers/bus/fslmc/fslmc_vfio.c +++ b/drivers/bus/fslmc/fslmc_vfio.c @@ -76,7 +76,7 @@ fslmc_get_container_group(int *groupid) if (!g_container) { container = getenv("DPRC"); if (container == NULL) { - RTE_LOG(WARNING, EAL, "DPAA2: DPRC not available\n"); + RTE_LOG(DEBUG, EAL, "DPAA2: DPRC not available\n"); return -EINVAL; } @@ -270,7 +270,7 @@ int rte_fslmc_vfio_dmamap(void) static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj) { - int64_t v_addr = (int64_t)MAP_FAILED; + intptr_t v_addr = (intptr_t)MAP_FAILED; int32_t ret, mc_fd; struct vfio_device_info d_info = { .argsz = sizeof(d_info) }; @@ -301,7 +301,7 @@ static int64_t vfio_map_mcp_obj(struct fslmc_vfio_group *group, char *mcp_obj) FSLMC_VFIO_LOG(DEBUG, "region offset = %llx , region size = %llx", reg_info.offset, reg_info.size); - v_addr = (uint64_t)mmap(NULL, reg_info.size, + v_addr = (size_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, mc_fd, reg_info.offset); @@ -469,7 +469,7 @@ fslmc_process_iodevices(struct rte_dpaa2_device *dev) static int fslmc_process_mcp(struct rte_dpaa2_device *dev) { - int64_t v_addr; + intptr_t v_addr; char *dev_name; struct fsl_mc_io dpmng = {0}; struct mc_version mc_ver_info = {0}; @@ -489,7 +489,7 @@ fslmc_process_mcp(struct rte_dpaa2_device *dev) } v_addr = vfio_map_mcp_obj(&vfio_group, dev_name); - if (v_addr == (int64_t)MAP_FAILED) { + if (v_addr == (intptr_t)MAP_FAILED) { FSLMC_VFIO_LOG(ERR, "Error mapping region (errno = %d)", errno); free(rte_mcp_ptr_list); diff --git a/drivers/bus/fslmc/mc/fsl_mc_cmd.h b/drivers/bus/fslmc/mc/fsl_mc_cmd.h index a3c3e79..ac91961 100644 --- a/drivers/bus/fslmc/mc/fsl_mc_cmd.h +++ b/drivers/bus/fslmc/mc/fsl_mc_cmd.h @@ -27,7 +27,7 @@ #define le32_to_cpu rte_le_to_cpu_32 #define le16_to_cpu rte_le_to_cpu_16 -#define BITS_PER_LONG 64 +#define BITS_PER_LONG (__SIZEOF_LONG__ * 8) #define GENMASK(h, l) \ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c index eefde15..7b671ef 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -291,7 +291,7 @@ struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id) if (!dpio_dev) return NULL; - PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu", + PMD_DRV_LOG(DEBUG, "New Portal %p (%d) affined thread - %lu", dpio_dev, dpio_dev->index, syscall(SYS_gettid)); ret = dpaa2_configure_stashing(dpio_dev, cpu_id); @@ -314,8 +314,9 @@ dpaa2_affine_qbman_swp(void) return -1; if (dpaa2_io_portal[lcore_id].dpio_dev) { - PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared" - " between thread %lu and current %lu", + PMD_DRV_LOG(INFO, "DPAAPortal=%p (%d) is being shared" + " between thread %" PRIu64 " and current " + "%" PRIu64 "\n", dpaa2_io_portal[lcore_id].dpio_dev, dpaa2_io_portal[lcore_id].dpio_dev->index, dpaa2_io_portal[lcore_id].net_tid, @@ -326,7 +327,8 @@ dpaa2_affine_qbman_swp(void) [lcore_id].dpio_dev->ref_count); dpaa2_io_portal[lcore_id].net_tid = tid; - PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu", + PMD_DRV_LOG(DEBUG, "Old Portal=%p (%d)" + "affined thread - %" PRIu64 "\n", dpaa2_io_portal[lcore_id].dpio_dev, dpaa2_io_portal[lcore_id].dpio_dev->index, tid); @@ -360,8 +362,9 @@ dpaa2_affine_qbman_swp_sec(void) return -1; if (dpaa2_io_portal[lcore_id].sec_dpio_dev) { - PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared" - " between thread %lu and current %lu", + PMD_DRV_LOG(INFO, "DPAAPortal=%p (%d) is being shared" + " between thread %" PRIu64 " and current " + "%" PRIu64 "\n", dpaa2_io_portal[lcore_id].sec_dpio_dev, dpaa2_io_portal[lcore_id].sec_dpio_dev->index, dpaa2_io_portal[lcore_id].sec_tid, @@ -372,7 +375,8 @@ dpaa2_affine_qbman_swp_sec(void) [lcore_id].sec_dpio_dev->ref_count); dpaa2_io_portal[lcore_id].sec_tid = tid; - PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu", + PMD_DRV_LOG(DEBUG, "Old Portal=%p (%d) " + "affined thread - %" PRIu64 "\n", dpaa2_io_portal[lcore_id].sec_dpio_dev, dpaa2_io_portal[lcore_id].sec_dpio_dev->index, tid); @@ -427,7 +431,7 @@ dpaa2_create_dpio_device(int vdev_fd, } dpio_dev->ce_size = reg_info.size; - dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size, + dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, vdev_fd, reg_info.offset); @@ -439,7 +443,7 @@ dpaa2_create_dpio_device(int vdev_fd, } dpio_dev->ci_size = reg_info.size; - dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size, + dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size, PROT_WRITE | PROT_READ, MAP_SHARED, vdev_fd, reg_info.offset); diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index d421dbf..4a19d42 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -174,7 +174,7 @@ enum qbman_fd_format { }; /*Macros to define operations on FD*/ #define DPAA2_SET_FD_ADDR(fd, addr) do { \ - (fd)->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \ + (fd)->simple.addr_lo = lower_32_bits((size_t)(addr)); \ (fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \ } while (0) #define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length) @@ -193,33 +193,32 @@ enum qbman_fd_format { #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16)) #define DPAA2_SET_FD_FLC(fd, addr) do { \ - (fd)->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \ + (fd)->simple.flc_lo = lower_32_bits((size_t)(addr)); \ (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \ } while (0) #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len))) #define DPAA2_GET_FLE_ADDR(fle) \ (uint64_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo) #define DPAA2_SET_FLE_ADDR(fle, addr) do { \ - (fle)->addr_lo = lower_32_bits((uint64_t)addr); \ - (fle)->addr_hi = upper_32_bits((uint64_t)addr); \ + (fle)->addr_lo = lower_32_bits((size_t)addr); \ + (fle)->addr_hi = upper_32_bits((uint64_t)addr); \ } while (0) #define DPAA2_GET_FLE_CTXT(fle) \ - (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \ - (fle)->reserved[0]) + ((((uint64_t)((fle)->reserved[1])) << 32) + (fle)->reserved[0]) #define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \ - (fle)->reserved[0] = lower_32_bits((uint64_t)addr); \ - (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \ + (fle)->reserved[0] = lower_32_bits((size_t)addr); \ + (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \ } while (0) #define DPAA2_SET_FLE_OFFSET(fle, offset) \ ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16) -#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid) +#define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (size_t)bpid) #define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff) -#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 31) +#define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= 1 << 31) #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000)) #define DPAA2_SET_FD_COMPOUND_FMT(fd) \ ((fd)->simple.bpid_offset |= (uint32_t)1 << 28) #define DPAA2_GET_FD_ADDR(fd) \ -((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo)) +(((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo)) #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len) #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF)) @@ -231,7 +230,7 @@ enum qbman_fd_format { (((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0) #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \ - ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size))) + ((struct rte_mbuf *)((size_t)(buf) - (meta_data_size))) #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64) @@ -265,14 +264,14 @@ static void *dpaa2_mem_ptov(phys_addr_t paddr) int i; if (dpaa2_virt_mode) - return (void *)paddr; + return (void *)(size_t)paddr; memseg = rte_eal_get_physmem_layout(); for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) { if (paddr >= memseg[i].iova && - (char *)paddr < (char *)memseg[i].iova + memseg[i].len) - return (void *)(memseg[i].addr_64 + paddr < memseg[i].iova + memseg[i].len) + return (void *)(size_t)(memseg[i].addr_64 + (paddr - memseg[i].iova)); } return NULL; @@ -295,7 +294,7 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) return memseg[i].iova + (vaddr - memseg[i].addr_64); } - return (phys_addr_t)(NULL); + return (size_t)(NULL); } /** @@ -311,18 +310,18 @@ static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) /** * macro to convert Virtual address to IOVA */ -#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr)) +#define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((size_t)(_vaddr)) /** * macro to convert IOVA to Virtual address */ -#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova)) +#define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((size_t)(_iova)) /** * macro to convert modify the memory containing IOVA to Virtual address */ #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \ - {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); } + {_mem = (_type)(dpaa2_mem_ptov((size_t)(_mem))); } #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */ diff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c index e221733..713ec96 100644 --- a/drivers/bus/fslmc/qbman/qbman_portal.c +++ b/drivers/bus/fslmc/qbman/qbman_portal.c @@ -553,10 +553,9 @@ int qbman_swp_enqueue_multiple(struct qbman_swp *s, /* Flush all the cacheline without load/store in between */ eqcr_pi = s->eqcr.pi; - addr_cena = (uint64_t)s->sys.addr_cena; + addr_cena = (size_t)s->sys.addr_cena; for (i = 0; i < num_enqueued; i++) { - dcbf((uint64_t *)(addr_cena + - QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); + dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); eqcr_pi++; eqcr_pi &= 0xF; } @@ -620,10 +619,9 @@ int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s, /* Flush all the cacheline without load/store in between */ eqcr_pi = s->eqcr.pi; - addr_cena = (uint64_t)s->sys.addr_cena; + addr_cena = (size_t)s->sys.addr_cena; for (i = 0; i < num_enqueued; i++) { - dcbf((uint64_t *)(addr_cena + - QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); + dcbf((addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & 7))); eqcr_pi++; eqcr_pi &= 0xF; } @@ -690,7 +688,7 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d, dma_addr_t storage_phys, int stash) { - d->pull.rsp_addr_virt = (uint64_t)storage; + d->pull.rsp_addr_virt = (size_t)storage; if (!storage) { d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT); @@ -749,7 +747,7 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d) } d->pull.tok = s->sys.idx + 1; - s->vdq.storage = (void *)d->pull.rsp_addr_virt; + s->vdq.storage = (void *)(size_t)d->pull.rsp_addr_virt; p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR); memcpy(&p[1], &cl[1], 12); diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 9a790dd..9a74845 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -77,11 +77,11 @@ build_proto_fd(dpaa2_sec_session *sess, DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src)); DPAA2_SET_FD_OFFSET(fd, sym_op->m_src->data_off); DPAA2_SET_FD_LEN(fd, sym_op->m_src->pkt_len); - DPAA2_SET_FD_FLC(fd, ((uint64_t)flc)); + DPAA2_SET_FD_FLC(fd, (ptrdiff_t)flc); /* save physical address of mbuf */ op->sym->aead.digest.phys_addr = mbuf->buf_iova; - mbuf->buf_iova = (uint64_t)op; + mbuf->buf_iova = (size_t)op; return 0; } @@ -118,7 +118,7 @@ build_authenc_gcm_sg_fd(dpaa2_sec_session *sess, } memset(fle, 0, FLE_SG_MEM_SIZE); DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (size_t)priv); op_fle = fle + 1; ip_fle = fle + 2; @@ -269,7 +269,7 @@ build_authenc_gcm_fd(dpaa2_sec_session *sess, } memset(fle, 0, FLE_POOL_BUF_SIZE); DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; sge = fle + 2; if (likely(bpid < MAX_BPID)) { @@ -414,7 +414,7 @@ build_authenc_sg_fd(dpaa2_sec_session *sess, } memset(fle, 0, FLE_SG_MEM_SIZE); DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); op_fle = fle + 1; ip_fle = fle + 2; @@ -563,7 +563,7 @@ build_authenc_fd(dpaa2_sec_session *sess, } memset(fle, 0, FLE_POOL_BUF_SIZE); DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; sge = fle + 2; if (likely(bpid < MAX_BPID)) { @@ -692,7 +692,7 @@ static inline int build_auth_sg_fd( memset(fle, 0, FLE_SG_MEM_SIZE); /* first FLE entry used to store mbuf and session ctxt */ DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); op_fle = fle + 1; ip_fle = fle + 2; sge = fle + 3; @@ -773,7 +773,7 @@ build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, * We can have a better approach to use the inline Mbuf */ DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; if (likely(bpid < MAX_BPID)) { @@ -865,7 +865,7 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, memset(fle, 0, FLE_SG_MEM_SIZE); /* first FLE entry used to store mbuf and session ctxt */ DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); op_fle = fle + 1; ip_fle = fle + 2; @@ -944,13 +944,13 @@ build_cipher_sg_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, DPAA2_SET_FD_COMPOUND_FMT(fd); DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc)); - PMD_TX_LOG(DEBUG, - "CIPHER SG: fdaddr =%p bpid =%d meta =%d off =%d, len =%d", - (void *)DPAA2_GET_FD_ADDR(fd), - DPAA2_GET_FD_BPID(fd), - rte_dpaa2_bpid_info[bpid].meta_data_size, - DPAA2_GET_FD_OFFSET(fd), - DPAA2_GET_FD_LEN(fd)); + PMD_TX_LOG(DEBUG, "CIPHER SG: fdaddr =%" PRIx64 + " bpid =%d meta =%d off =%d, len =%d\n", + DPAA2_GET_FD_ADDR(fd), + DPAA2_GET_FD_BPID(fd), + rte_dpaa2_bpid_info[bpid].meta_data_size, + DPAA2_GET_FD_OFFSET(fd), + DPAA2_GET_FD_LEN(fd)); return 0; } @@ -987,7 +987,7 @@ build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op, * We can have a better approach to use the inline Mbuf */ DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op)); - DPAA2_FLE_SAVE_CTXT(fle, priv); + DPAA2_FLE_SAVE_CTXT(fle, (ptrdiff_t)priv); fle = fle + 1; sge = fle + 2; @@ -1206,7 +1206,7 @@ sec_simple_fd_to_mbuf(const struct qbman_fd *fd, __rte_unused uint8_t id) DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)), rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size); - op = (struct rte_crypto_op *)mbuf->buf_iova; + op = (struct rte_crypto_op *)(size_t)mbuf->buf_iova; mbuf->buf_iova = op->sym->aead.digest.phys_addr; op->sym->aead.digest.phys_addr = 0L; @@ -1267,16 +1267,17 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, uint8_t driver_id) PMD_RX_LOG(DEBUG, "mbuf %p BMAN buf addr %p", (void *)dst, dst->buf_addr); - PMD_RX_LOG(DEBUG, "fdaddr =%p bpid =%d meta =%d off =%d, len =%d", - (void *)DPAA2_GET_FD_ADDR(fd), - DPAA2_GET_FD_BPID(fd), - rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, - DPAA2_GET_FD_OFFSET(fd), - DPAA2_GET_FD_LEN(fd)); + PMD_RX_LOG(DEBUG, "fdaddr =%" PRIx64 + " bpid =%d meta =%d off =%d, len =%d", + DPAA2_GET_FD_ADDR(fd), + DPAA2_GET_FD_BPID(fd), + rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, + DPAA2_GET_FD_OFFSET(fd), + DPAA2_GET_FD_LEN(fd)); /* free the fle memory */ if (likely(rte_pktmbuf_is_contiguous(src))) { - priv = (struct ctxt_priv *)DPAA2_GET_FLE_CTXT(fle - 1); + priv = (struct ctxt_priv *)(size_t)DPAA2_GET_FLE_CTXT(fle - 1); rte_mempool_put(priv->fle_pool, (void *)(fle-1)); } else rte_free((void *)(fle-1)); @@ -1455,7 +1456,7 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, dev->data->queue_pairs[qp_id] = qp; cfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX; - cfg.user_ctx = (uint64_t)(&qp->rx_vq); + cfg.user_ctx = (size_t)(&qp->rx_vq); retcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token, qp_id, &cfg); return retcode; @@ -1536,7 +1537,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, memcpy(session->cipher_key.data, xform->cipher.key.data, xform->cipher.key.length); - cipherdata.key = (uint64_t)session->cipher_key.data; + cipherdata.key = (size_t)session->cipher_key.data; cipherdata.keylen = session->cipher_key.length; cipherdata.key_enc_flags = 0; cipherdata.key_type = RTA_DATA_IMM; @@ -1595,10 +1596,10 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); session->ctxt = priv; @@ -1651,7 +1652,7 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, memcpy(session->auth_key.data, xform->auth.key.data, xform->auth.key.length); - authdata.key = (uint64_t)session->auth_key.data; + authdata.key = (size_t)session->auth_key.data; authdata.keylen = session->auth_key.length; authdata.key_enc_flags = 0; authdata.key_type = RTA_DATA_IMM; @@ -1720,10 +1721,10 @@ dpaa2_sec_auth_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); session->ctxt = priv; for (i = 0; i < bufsize; i++) @@ -1786,7 +1787,7 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev, session->aead_key.length = aead_xform->key.length; ctxt->auth_only_len = aead_xform->aad_length; - aeaddata.key = (uint64_t)session->aead_key.data; + aeaddata.key = (size_t)session->aead_key.data; aeaddata.keylen = session->aead_key.length; aeaddata.key_enc_flags = 0; aeaddata.key_type = RTA_DATA_IMM; @@ -1840,10 +1841,10 @@ dpaa2_sec_aead_init(struct rte_cryptodev *dev, session->digest_length); flc->word1_sdl = (uint8_t)bufsize; flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); session->ctxt = priv; for (i = 0; i < bufsize; i++) @@ -1928,7 +1929,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, memcpy(session->auth_key.data, auth_xform->key.data, auth_xform->key.length); - authdata.key = (uint64_t)session->auth_key.data; + authdata.key = (size_t)session->auth_key.data; authdata.keylen = session->auth_key.length; authdata.key_enc_flags = 0; authdata.key_type = RTA_DATA_IMM; @@ -1988,7 +1989,7 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, auth_xform->algo); goto error_out; } - cipherdata.key = (uint64_t)session->cipher_key.data; + cipherdata.key = (size_t)session->cipher_key.data; cipherdata.keylen = session->cipher_key.length; cipherdata.key_enc_flags = 0; cipherdata.key_type = RTA_DATA_IMM; @@ -2066,10 +2067,10 @@ dpaa2_sec_aead_chain_init(struct rte_cryptodev *dev, flc->word1_sdl = (uint8_t)bufsize; flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); session->ctxt = priv; for (i = 0; i < bufsize; i++) @@ -2202,7 +2203,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev, memcpy(session->auth_key.data, auth_xform->key.data, auth_xform->key.length); - authdata.key = (uint64_t)session->auth_key.data; + authdata.key = (size_t)session->auth_key.data; authdata.keylen = session->auth_key.length; authdata.key_enc_flags = 0; authdata.key_type = RTA_DATA_IMM; @@ -2261,7 +2262,7 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev, auth_xform->algo); goto out; } - cipherdata.key = (uint64_t)session->cipher_key.data; + cipherdata.key = (size_t)session->cipher_key.data; cipherdata.keylen = session->cipher_key.length; cipherdata.key_enc_flags = 0; cipherdata.key_type = RTA_DATA_IMM; @@ -2345,10 +2346,10 @@ dpaa2_sec_set_ipsec_session(struct rte_cryptodev *dev, /* Enable the stashing control bit */ DPAA2_SET_FLC_RSC(flc); flc->word2_rflc_31_0 = lower_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq) | 0x14); flc->word3_rflc_63_32 = upper_32_bits( - (uint64_t)&(((struct dpaa2_sec_qp *) + (size_t)&(((struct dpaa2_sec_qp *) dev->data->queue_pairs[0])->rx_vq)); /* Set EWS bit i.e. enable write-safe */ @@ -2647,13 +2648,13 @@ void dpaa2_sec_stats_get(struct rte_cryptodev *dev, PMD_DRV_LOG(ERR, "dpseci_get_sec_counters failed\n"); } else { PMD_DRV_LOG(INFO, "dpseci hw stats:" - "\n\tNumber of Requests Dequeued = %lu" - "\n\tNumber of Outbound Encrypt Requests = %lu" - "\n\tNumber of Inbound Decrypt Requests = %lu" - "\n\tNumber of Outbound Bytes Encrypted = %lu" - "\n\tNumber of Outbound Bytes Protected = %lu" - "\n\tNumber of Inbound Bytes Decrypted = %lu" - "\n\tNumber of Inbound Bytes Validated = %lu", + "\n\tNumber of Requests Dequeued = %" PRIu64 + "\n\tNumber of Outbound Encrypt Requests = %" PRIu64 + "\n\tNumber of Inbound Decrypt Requests = %" PRIu64 + "\n\tNumber of Outbound Bytes Encrypted = %" PRIu64 + "\n\tNumber of Outbound Bytes Protected = %" PRIu64 + "\n\tNumber of Inbound Bytes Decrypted = %" PRIu64 + "\n\tNumber of Inbound Bytes Validated = %" PRIu64, counters.dequeued_requests, counters.ob_enc_requests, counters.ib_dec_requests, diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index c3e6fbf..8800b47 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -126,7 +126,7 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[], goto send_partial; } rte_memcpy(ev_temp, event, sizeof(struct rte_event)); - DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp); + DPAA2_SET_FD_ADDR((&fd_arr[loop]), (size_t)ev_temp); DPAA2_SET_FD_LEN((&fd_arr[loop]), sizeof(struct rte_event)); } @@ -182,7 +182,7 @@ static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp, struct rte_event *ev) { struct rte_event *ev_temp = - (struct rte_event *)DPAA2_GET_FD_ADDR(fd); + (struct rte_event *)(size_t)DPAA2_GET_FD_ADDR(fd); RTE_SET_USED(rxq); @@ -199,7 +199,7 @@ static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp, struct rte_event *ev) { struct rte_event *ev_temp = - (struct rte_event *)DPAA2_GET_FD_ADDR(fd); + (struct rte_event *)(size_t)DPAA2_GET_FD_ADDR(fd); uint8_t dqrr_index = qbman_get_dqrr_idx(dq); RTE_SET_USED(swp); @@ -258,7 +258,7 @@ dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[], qbman_swp_prefetch_dqrr_next(swp); fd = qbman_result_DQ_fd(dq); - rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq); + rxq = (struct dpaa2_queue *)(size_t)qbman_result_DQ_fqd_ctx(dq); if (rxq) { rxq->cb(swp, fd, dq, rxq, &ev[num_pkts]); } else { @@ -736,7 +736,7 @@ dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev, dpaa2_eventdev_process_atomic; for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) { - rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]); + rx_queue_cfg.user_ctx = (size_t)(&dpci_dev->queue[i]); ret = dpci_set_rx_queue(&dpci_dev->dpci, CMD_PRI_LOW, dpci_dev->token, i, diff --git a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c index 2bd62e8..1a618ae 100644 --- a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c +++ b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c @@ -242,7 +242,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, #endif struct qbman_swp *swp; uint16_t bpid; - uint64_t bufs[DPAA2_MBUF_MAX_ACQ_REL]; + size_t bufs[DPAA2_MBUF_MAX_ACQ_REL]; int i, ret; unsigned int n = 0; struct dpaa2_bp_info *bp_info; @@ -270,10 +270,10 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, * then the remainder. */ if ((count - n) > DPAA2_MBUF_MAX_ACQ_REL) { - ret = qbman_swp_acquire(swp, bpid, bufs, + ret = qbman_swp_acquire(swp, bpid, (void *)bufs, DPAA2_MBUF_MAX_ACQ_REL); } else { - ret = qbman_swp_acquire(swp, bpid, bufs, + ret = qbman_swp_acquire(swp, bpid, (void *)bufs, count - n); } /* In case of less than requested number of buffers available @@ -290,7 +290,7 @@ rte_dpaa2_mbuf_alloc_bulk(struct rte_mempool *pool, } /* assigning mbuf from the acquired objects */ for (i = 0; (i < ret) && bufs[i]; i++) { - DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], uint64_t); + DPAA2_MODIFY_IOVA_TO_VADDR(bufs[i], size_t); obj_table[n] = (struct rte_mbuf *) (bufs[i] - bp_info->meta_data_size); PMD_TX_LOG(DEBUG, "Acquired %p address %p from BMAN", diff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile index 5a93a0b..068e9d3 100644 --- a/drivers/net/dpaa2/Makefile +++ b/drivers/net/dpaa2/Makefile @@ -25,7 +25,6 @@ CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/qbman/include CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/portal CFLAGS += -I$(RTE_SDK)/drivers/mempool/dpaa2 -CFLAGS += -I$(RTE_SDK)/drivers/event/dpaa2 CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal # versioning export map diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c index b93376d..4b60f56 100644 --- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c +++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c @@ -50,7 +50,7 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, ret = dpaa2_distset_to_dpkg_profile_cfg(req_dist_set, &kg_cfg); if (ret) { - PMD_INIT_LOG(ERR, "given rss_hf (%lx) not supported", + PMD_INIT_LOG(ERR, "given rss_hf (%" PRIx64 ") not supported", req_dist_set); rte_free(p_params); return ret; diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c index 09a11d6..fd5897e 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.c +++ b/drivers/net/dpaa2/dpaa2_ethdev.c @@ -445,7 +445,7 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, memset(&cfg, 0, sizeof(struct dpni_queue)); options = options | DPNI_QUEUE_OPT_USER_CTX; - cfg.user_context = (uint64_t)(dpaa2_q); + cfg.user_context = (size_t)(dpaa2_q); /*if ls2088 or rev2 device, enable the stashing */ @@ -560,7 +560,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, */ cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD; cong_notif_cfg.message_ctx = 0; - cong_notif_cfg.message_iova = (uint64_t)dpaa2_q->cscn; + cong_notif_cfg.message_iova = (size_t)dpaa2_q->cscn; cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; cong_notif_cfg.notification_mode = DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | @@ -1702,7 +1702,7 @@ int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, } options |= DPNI_QUEUE_OPT_USER_CTX; - cfg.user_context = (uint64_t)(dpaa2_ethq); + cfg.user_context = (size_t)(dpaa2_ethq); ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, dpaa2_ethq->tc_index, flow_id, options, &cfg); diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index 183293c..21a08b6 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -21,7 +21,6 @@ #include #include #include -#include #include "dpaa2_ethdev.h" #include "base/dpaa2_hw_dpni_annot.h" @@ -104,13 +103,11 @@ dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc) } static inline uint32_t __attribute__((hot)) -dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr) +dpaa2_dev_rx_parse_slow(struct dpaa2_annot_hdr *annotation) { uint32_t pkt_type = RTE_PTYPE_UNKNOWN; - struct dpaa2_annot_hdr *annotation = - (struct dpaa2_annot_hdr *)hw_annot_addr; - PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4); + PMD_RX_LOG(DEBUG, "annotation = 0x%" PRIx64, annotation->word4); if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) { pkt_type = RTE_PTYPE_L2_ETHER_ARP; goto parse_done; @@ -167,12 +164,12 @@ dpaa2_dev_rx_parse_slow(uint64_t hw_annot_addr) } static inline uint32_t __attribute__((hot)) -dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr) +dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, void *hw_annot_addr) { struct dpaa2_annot_hdr *annotation = (struct dpaa2_annot_hdr *)hw_annot_addr; - PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4); + PMD_RX_LOG(DEBUG, "annotation = 0x%" PRIx64, annotation->word4); /* Check offloads first */ if (BIT_ISSET_AT_POS(annotation->word3, @@ -207,25 +204,24 @@ dpaa2_dev_rx_parse(struct rte_mbuf *mbuf, uint64_t hw_annot_addr) break; } - return dpaa2_dev_rx_parse_slow(hw_annot_addr); + return dpaa2_dev_rx_parse_slow(annotation); } static inline struct rte_mbuf *__attribute__((hot)) eth_sg_fd_to_mbuf(const struct qbman_fd *fd) { struct qbman_sge *sgt, *sge; - dma_addr_t sg_addr; + size_t sg_addr, fd_addr; int i = 0; - uint64_t fd_addr; struct rte_mbuf *first_seg, *next_seg, *cur_seg, *temp; - fd_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); + fd_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); /* Get Scatter gather table address */ sgt = (struct qbman_sge *)(fd_addr + DPAA2_GET_FD_OFFSET(fd)); sge = &sgt[i++]; - sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge)); + sg_addr = (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FLE_ADDR(sge)); /* First Scatter gather entry */ first_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr, @@ -243,14 +239,14 @@ eth_sg_fd_to_mbuf(const struct qbman_fd *fd) DPAA2_GET_FD_FRC_PARSE_SUM(fd)); else first_seg->packet_type = dpaa2_dev_rx_parse(first_seg, - (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) - + DPAA2_FD_PTA_SIZE); + (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + + DPAA2_FD_PTA_SIZE)); rte_mbuf_refcnt_set(first_seg, 1); cur_seg = first_seg; while (!DPAA2_SG_IS_FINAL(sge)) { sge = &sgt[i++]; - sg_addr = (uint64_t)DPAA2_IOVA_TO_VADDR( + sg_addr = (size_t)DPAA2_IOVA_TO_VADDR( DPAA2_GET_FLE_ADDR(sge)); next_seg = DPAA2_INLINE_MBUF_FROM_BUF(sg_addr, rte_dpaa2_bpid_info[DPAA2_GET_FLE_BPID(sge)].meta_data_size); @@ -299,12 +295,12 @@ eth_fd_to_mbuf(const struct qbman_fd *fd) dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd)); else mbuf->packet_type = dpaa2_dev_rx_parse(mbuf, - (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) - + DPAA2_FD_PTA_SIZE); + (void *)((size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + + DPAA2_FD_PTA_SIZE)); PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d," - "fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n", - mbuf, mbuf->buf_addr, mbuf->data_off, + "fd_off=%d fd =%" PRIx64 ", meta = %d bpid =%d, len=%d\n", + (void *)mbuf, (void *)mbuf->buf_addr, mbuf->data_off, DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd), rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd)); @@ -340,7 +336,7 @@ eth_mbuf_to_sg_fd(struct rte_mbuf *mbuf, DPAA2_FD_SET_FORMAT(fd, qbman_fd_sg); /*Set Scatter gather table and Scatter gather entries*/ sgt = (struct qbman_sge *)( - (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + (size_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + DPAA2_GET_FD_OFFSET(fd)); for (i = 0; i < mbuf->nb_segs; i++) { @@ -402,8 +398,8 @@ eth_mbuf_to_fd(struct rte_mbuf *mbuf, DPAA2_MBUF_TO_CONTIG_FD(mbuf, fd, bpid); PMD_TX_LOG(DEBUG, "mbuf =%p, mbuf->buf_addr =%p, off = %d," - "fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n", - mbuf, mbuf->buf_addr, mbuf->data_off, + "fd_off=%d fd =%" PRIx64 ", meta = %d bpid =%d, len=%d\n", + (void *)mbuf, mbuf->buf_addr, mbuf->data_off, DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd), rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd)); @@ -458,11 +454,12 @@ eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf, PMD_TX_LOG(DEBUG, " mbuf %p BMAN buf addr %p", (void *)mbuf, mbuf->buf_addr); - PMD_TX_LOG(DEBUG, " fdaddr =%lx bpid =%d meta =%d off =%d, len =%d", - DPAA2_GET_FD_ADDR(fd), - DPAA2_GET_FD_BPID(fd), - rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, + PMD_TX_LOG(DEBUG, + "fd_off=%d fd =%" PRIx64 ", meta = %d bpid =%d, len=%d\n", DPAA2_GET_FD_OFFSET(fd), + DPAA2_GET_FD_ADDR(fd), + rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, + DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd)); return 0; @@ -523,8 +520,8 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) } dq_storage = q_storage->active_dqs; - rte_prefetch0((void *)((uint64_t)(dq_storage))); - rte_prefetch0((void *)((uint64_t)(dq_storage + 1))); + rte_prefetch0((void *)(size_t)(dq_storage)); + rte_prefetch0((void *)(size_t)(dq_storage + 1)); /* Prepare next pull descriptor. This will give space for the * prefething done on DQRR entries @@ -554,7 +551,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) */ while (!qbman_check_new_result(dq_storage)) ; - rte_prefetch0((void *)((uint64_t)(dq_storage + 2))); + rte_prefetch0((void *)((size_t)(dq_storage + 2))); /* Check whether Last Pull command is Expired and * setting Condition for Loop termination */ @@ -569,7 +566,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) next_fd = qbman_result_DQ_fd(dq_storage + 1); /* Prefetch Annotation address for the parse results */ - rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(next_fd) + rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(next_fd) + DPAA2_FD_PTA_SIZE + 16)); if (unlikely(DPAA2_FD_GET_FORMAT(fd) == qbman_fd_sg)) @@ -616,7 +613,7 @@ dpaa2_dev_process_parallel_event(struct qbman_swp *swp, struct dpaa2_queue *rxq, struct rte_event *ev) { - rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(fd) + + rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) + DPAA2_FD_PTA_SIZE + 16)); ev->flow_id = rxq->ev.flow_id; @@ -641,7 +638,7 @@ dpaa2_dev_process_atomic_event(struct qbman_swp *swp __attribute__((unused)), { uint8_t dqrr_index; - rte_prefetch0((void *)(DPAA2_GET_FD_ADDR(fd) + + rte_prefetch0((void *)(size_t)(DPAA2_GET_FD_ADDR(fd) + DPAA2_FD_PTA_SIZE + 16)); ev->flow_id = rxq->ev.flow_id; @@ -726,7 +723,7 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) fd_arr[loop].simple.frc = 0; DPAA2_RESET_FD_CTRL((&fd_arr[loop])); - DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL); + DPAA2_SET_FD_FLC((&fd_arr[loop]), (size_t)NULL); if (likely(RTE_MBUF_DIRECT(*bufs))) { mp = (*bufs)->pool; /* Check the basic scenario and set