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Thu, 7 Dec 2017 22:22:46 -0700 From: Hemant Agrawal To: CC: , , Nipun Gupta , Ashish Jain Date: Fri, 8 Dec 2017 10:51:24 +0530 Message-ID: <1512710487-32388-12-git-send-email-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512710487-32388-1-git-send-email-hemant.agrawal@nxp.com> References: <1512710487-32388-1-git-send-email-hemant.agrawal@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131571841688643786; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(7966004)(336005)(376002)(39380400002)(346002)(39860400002)(2980300002)(1109001)(1110001)(339900001)(199004)(189003)(48376002)(68736007)(356003)(8936002)(47776003)(50226002)(305945005)(498600001)(5660300001)(36756003)(316002)(53936002)(6916009)(77096006)(2950100002)(104016004)(6666003)(54906003)(86362001)(85426001)(2906002)(8676002)(575784001)(76176011)(50466002)(16586007)(4326008)(81166006)(51416003)(97736004)(8656006)(81156014)(296002)(106466001)(2351001)(33646002)(105606002); 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2700 Subject: [dpdk-dev] [PATCH 11/14] net/dpaa2: add parse function for LX2 device X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nipun Gupta Adding support for DPDK packet parsing logic for LX2 platform to accomodate the new FRC format introduced in LX2. Signed-off-by: Ashish Jain Signed-off-by: Nipun Gupta --- drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 2 + drivers/net/dpaa2/dpaa2_ethdev.h | 27 ++++++++++ drivers/net/dpaa2/dpaa2_rxtx.c | 94 ++++++++++++++++++++++++++++++--- 3 files changed, 116 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index 9f9ce0b..c29d7f3 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -209,6 +209,8 @@ enum qbman_fd_format { (((fd)->simple.bpid_offset |= (uint32_t)(offset) << 16)) #define DPAA2_SET_FD_INTERNAL_JD(fd, len) \ ((fd)->simple.frc = (0x80000000 | (len))) +#define DPAA2_GET_FD_FRC_PARSE_SUM(fd) \ + ((uint16_t)(((fd)->simple.frc & 0xffff0000) >> 16)) #define DPAA2_SET_FD_FRC(fd, frc) ((fd)->simple.frc = frc) #define DPAA2_RESET_FD_CTRL(fd) ((fd)->simple.ctrl = 0) diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h index b8e94aa..9a9496f 100644 --- a/drivers/net/dpaa2/dpaa2_ethdev.h +++ b/drivers/net/dpaa2/dpaa2_ethdev.h @@ -76,6 +76,33 @@ /* Disable RX tail drop, default is enable */ #define DPAA2_RX_TAILDROP_OFF 0x04 +/* LX2 FRC Parsed values (Little Endian) */ +#define DPAA2_PKT_TYPE_ETHER 0x0060 +#define DPAA2_PKT_TYPE_IPV4 0x0000 +#define DPAA2_PKT_TYPE_IPV6 0x0020 +#define DPAA2_PKT_TYPE_IPV4_EXT \ + (0x0001 | DPAA2_PKT_TYPE_IPV4) +#define DPAA2_PKT_TYPE_IPV6_EXT \ + (0x0001 | DPAA2_PKT_TYPE_IPV6) +#define DPAA2_PKT_TYPE_IPV4_TCP \ + (0x000e | DPAA2_PKT_TYPE_IPV4) +#define DPAA2_PKT_TYPE_IPV6_TCP \ + (0x000e | DPAA2_PKT_TYPE_IPV6) +#define DPAA2_PKT_TYPE_IPV4_UDP \ + (0x0010 | DPAA2_PKT_TYPE_IPV4) +#define DPAA2_PKT_TYPE_IPV6_UDP \ + (0x0010 | DPAA2_PKT_TYPE_IPV6) +#define DPAA2_PKT_TYPE_IPV4_SCTP \ + (0x000f | DPAA2_PKT_TYPE_IPV4) +#define DPAA2_PKT_TYPE_IPV6_SCTP \ + (0x000f | DPAA2_PKT_TYPE_IPV6) +#define DPAA2_PKT_TYPE_IPV4_ICMP \ + (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT) +#define DPAA2_PKT_TYPE_IPV6_ICMP \ + (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT) +#define DPAA2_PKT_TYPE_VLAN_1 0x0160 +#define DPAA2_PKT_TYPE_VLAN_2 0x0260 + struct dpaa2_dev_priv { void *hw; int32_t hw_id; diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c index 93c2319..3b58a48 100644 --- a/drivers/net/dpaa2/dpaa2_rxtx.c +++ b/drivers/net/dpaa2/dpaa2_rxtx.c @@ -50,6 +50,75 @@ #include "dpaa2_ethdev.h" #include "base/dpaa2_hw_dpni_annot.h" +static inline void __attribute__((hot)) +dpaa2_dev_rx_parse_frc(struct rte_mbuf *m, uint16_t frc) +{ + PMD_RX_LOG(DEBUG, "frc = 0x%x ", frc); + + m->packet_type = RTE_PTYPE_UNKNOWN; + switch (frc) { + case DPAA2_PKT_TYPE_ETHER: + m->packet_type = RTE_PTYPE_L2_ETHER; + break; + case DPAA2_PKT_TYPE_IPV4: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4; + break; + case DPAA2_PKT_TYPE_IPV6: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6; + break; + case DPAA2_PKT_TYPE_IPV4_EXT: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4_EXT; + break; + case DPAA2_PKT_TYPE_IPV6_EXT: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6_EXT; + break; + case DPAA2_PKT_TYPE_IPV4_TCP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP; + break; + case DPAA2_PKT_TYPE_IPV6_TCP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP; + break; + case DPAA2_PKT_TYPE_IPV4_UDP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP; + break; + case DPAA2_PKT_TYPE_IPV6_UDP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP; + break; + case DPAA2_PKT_TYPE_IPV4_SCTP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP; + break; + case DPAA2_PKT_TYPE_IPV6_SCTP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_SCTP; + break; + case DPAA2_PKT_TYPE_IPV4_ICMP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_ICMP; + break; + case DPAA2_PKT_TYPE_IPV6_ICMP: + m->packet_type = RTE_PTYPE_L2_ETHER | + RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_ICMP; + break; + case DPAA2_PKT_TYPE_VLAN_1: + case DPAA2_PKT_TYPE_VLAN_2: + m->ol_flags |= PKT_RX_VLAN; + break; + /* More switch cases can be added */ + /* TODO: Add handling for checksum error check from FRC */ + default: + m->packet_type = RTE_PTYPE_UNKNOWN; + } +} + static inline uint32_t __attribute__((hot)) dpaa2_dev_rx_parse(uint64_t hw_annot_addr) { @@ -159,13 +228,17 @@ eth_sg_fd_to_mbuf(const struct qbman_fd *fd) first_seg->pkt_len = DPAA2_GET_FD_LEN(fd); first_seg->nb_segs = 1; first_seg->next = NULL; - - first_seg->packet_type = dpaa2_dev_rx_parse( + if (dpaa2_svr_family == SVR_LX2160A) + dpaa2_dev_rx_parse_frc(first_seg, + DPAA2_GET_FD_FRC_PARSE_SUM(fd)); + else { + first_seg->packet_type = dpaa2_dev_rx_parse( (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + DPAA2_FD_PTA_SIZE); - dpaa2_dev_rx_offload((uint64_t)DPAA2_IOVA_TO_VADDR( + dpaa2_dev_rx_offload((uint64_t)DPAA2_IOVA_TO_VADDR( DPAA2_GET_FD_ADDR(fd)) + DPAA2_FD_PTA_SIZE, first_seg); + } rte_mbuf_refcnt_set(first_seg, 1); cur_seg = first_seg; while (!DPAA2_SG_IS_FINAL(sge)) { @@ -208,14 +281,21 @@ eth_fd_to_mbuf(const struct qbman_fd *fd) mbuf->pkt_len = mbuf->data_len; /* Parse the packet */ - /* parse results are after the private - sw annotation area */ - mbuf->packet_type = dpaa2_dev_rx_parse( + /* parse results for LX2 are there in FRC field of FD. + * For other DPAA2 platforms , parse results are after + * the private - sw annotation area + */ + + if (dpaa2_svr_family == SVR_LX2160A) + dpaa2_dev_rx_parse_frc(mbuf, DPAA2_GET_FD_FRC_PARSE_SUM(fd)); + else { + mbuf->packet_type = dpaa2_dev_rx_parse( (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) + DPAA2_FD_PTA_SIZE); - - dpaa2_dev_rx_offload((uint64_t)DPAA2_IOVA_TO_VADDR( + dpaa2_dev_rx_offload((uint64_t)DPAA2_IOVA_TO_VADDR( DPAA2_GET_FD_ADDR(fd)) + DPAA2_FD_PTA_SIZE, mbuf); + } mbuf->next = NULL; rte_mbuf_refcnt_set(mbuf, 1);