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[209.132.180.131]) by mx.google.com with ESMTPS id bb1si671000pbc.69.2015.11.09.15.36.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Nov 2015 15:36:45 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-return-89647-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-return-89647-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=binutils-return-89647-patch=linaro.org@sourceware.org; dkim=pass header.i=@sourceware.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:date:message-id:subject:from:to :content-type; q=dns; s=default; b=pH/gSV4clPtZC3BS1DEn0PSzkPK6+ FhQEkNI/mqcbPRGWmSjURbdhHPbebUTU7UY/+22Ql5A8hxvGUFzuS9H2tFBqMj4+ HMvpVM822xK3Kd94Xuv6Go8zoBIVtsfybCjdJxKaEH4ODEnTC1OBdCZiYfHIkdPg 3Y6ITFJ5KoYpww= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:date:message-id:subject:from:to :content-type; s=default; bh=pUkZ5rv7V/RaXlUP9BVEaNfrUfw=; b=ZyR Mu8M0epOKmzWQ7EAJlaE5stwtEVZsrYDx/pAuhTCGfYnbN64pqhIPaskyn4lxF78 YsP/N4TvtEobwD3uX4vofEg8qliyW95N9ePOoYKTAopAdhNrEM2K/b6GMqNxIjVF GAVkDZE4BUJW4hSaVAGC3aO+Cb2gPuEkqiMjQWwM= Received: (qmail 65788 invoked by alias); 9 Nov 2015 23:36:32 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Delivered-To: mailing list binutils@sourceware.org Received: (qmail 65773 invoked by uid 89); 9 Nov 2015 23:36:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f172.google.com Received: from mail-ob0-f172.google.com (HELO mail-ob0-f172.google.com) (209.85.214.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 09 Nov 2015 23:36:30 +0000 Received: by obbww6 with SMTP id ww6so126137661obb.0 for ; Mon, 09 Nov 2015 15:36:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:date:message-id:subject:from:to :content-type; bh=lBCweNXDK7fvAtMxI8RT6+7rx6b+PvjN9Uh16zGJRS8=; b=m8Yy/WssrrTDYwpmmq1SF9XgT2ZRrfDyhtcGCtM2LnlixrgyAcUyxEi/+FEkgFzo+l tsiEZ4uDtJSQF7rqsJ7BTwvDmhX+mZgP6e7TbHYmsV+RC1ff03k68fBhOUU4ewmvPQ7x p1EGkzvNKqkT285MbTXw76fGWaY5Brbf+31adknm89kJo9GvWcwZzOynPwErIusRlybk c8+rPoswdyoSSMvWKoPGqcoYA7bv136o7eLHLOnm0Ar+1LUvAm4NqralfJWCR2t1I/Lv MfxnejzuDZeH6RltOS42CG3dV0HyJa9UviAZi0ymLzWAccwLQD5jmLJGoml5iJsH3LR9 HUww== X-Gm-Message-State: ALoCoQn7j25+g4Gd/hDwamwUE3Yy1qeJC0Oh3Uh7b9vo8/YMcdczxckPxprFXNX6J93FsLvPkBJ7 MIME-Version: 1.0 X-Received: by 10.182.131.132 with SMTP id om4mr301176obb.72.1447112188662; Mon, 09 Nov 2015 15:36:28 -0800 (PST) Received: by 10.76.93.197 with HTTP; Mon, 9 Nov 2015 15:36:28 -0800 (PST) Date: Mon, 9 Nov 2015 15:36:28 -0800 Message-ID: Subject: [PATCH] [ARM/AARCH64] add initial Qualcomm processor support From: Jim Wilson To: Binutils This patch adds initial support for the Qualcomm qdf24xx server chips. This was tested with armhf and aarch64 cross builds and make check. Jim gas/ChangeLog | 6 ++++++ gas/config/tc-aarch64.c | 3 +++ gas/config/tc-arm.c | 4 ++++ gas/doc/c-aarch64.texi | 1 + gas/doc/c-arm.texi | 1 + 5 files changed, 15 insertions(+) diff --git a/gas/ChangeLog b/gas/ChangeLog index 2214ed3..2aaf0b7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2015-11-09 Jim Wilson + + * config/tc-aarch64.c (aarch64_cpus): Add qdf24xx. + * config/tc-arm.c (arm_cpus): Likewise. + * doc/c-arm.texi, doc/c-aarch64.texi: Likewise. + 2015-11-09 Dominik Vogt * read.c (parse_bitfield_cons): Fix left shift of negative value. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2cc7b4b..b45aac8 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7685,6 +7685,9 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = { {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8, AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), "Samsung Exynos M1"}, + {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8, + AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), + "Qualcomm QDF24XX"}, {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8, AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), "Cavium ThunderX"}, diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index de99d72..e33a77f 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -24743,6 +24743,10 @@ static const struct arm_cpu_option_table arm_cpus[] = ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, "Samsung " \ "Exynos M1"), + ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, + "Qualcomm " + "QDF24XX"), + /* ??? XSCALE is really an architecture. */ ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL), /* ??? iwmmxt is not a processor. */ diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 2053990..e3ca09d 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -59,6 +59,7 @@ on the target processor. The following processor names are recognized: @code{cortex-a57}, @code{cortex-a72}, @code{exynos-m1}, +@code{qdf24xx}, @code{thunderx}, @code{xgene1} and diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index e41943b..661f631 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -135,6 +135,7 @@ recognized: @code{exynos-m1}, @code{marvell-pj4}, @code{marvell-whitney}, +@code{qdf24xx}, @code{xgene1}, @code{xgene2}, @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),