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[77.48.224.243]) by mx.google.com with ESMTP id a9si44341wrf.414.2018.02.22.05.17.15; Thu, 22 Feb 2018 05:17:16 -0800 (PST) Received-SPF: pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) client-ip=77.48.224.243; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=vcNREQ0J; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 6B2FC267753; Thu, 22 Feb 2018 14:16:41 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 20E31267749; Thu, 22 Feb 2018 14:16:39 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, SPF_PASS, T_RP_MATCHES_RCVD autolearn=disabled version=3.4.0 Received: from heliosphere.sirena.org.uk (heliosphere.sirena.org.uk [172.104.155.198]) by alsa0.perex.cz (Postfix) with ESMTP id C338026773D for ; Thu, 22 Feb 2018 14:16:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=BEesEPpFJb4VP2Eju1HqJWs7ctwT1tH8MR5KmFTjz5M=; b=vcNREQ0JtLof BnukHttwOEL014yNRN03KWexvbIDbjm5H+FnqAWHB5DA0TWA3nhKAXg7yHL089F9i7Lo1nclxPXB4 h6k0ZaDtKXFdGIH7Xs5v6c/JtsiR9OiP02GGfG4mknFn2RD0Qo7+iL2tH/kn5eMXmSmLdRzl3bFog ksBLA=; Received: from debutante.sirena.org.uk ([2001:470:1f1d:6b5::3] helo=debutante) by heliosphere.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1eoqjV-0002TG-GL; Thu, 22 Feb 2018 13:16:21 +0000 Received: from broonie by debutante with local (Exim 4.90_1) (envelope-from ) id 1eoqjU-0006Ed-V7; Thu, 22 Feb 2018 13:16:20 +0000 From: Mark Brown To: Nicolin Chen In-Reply-To: <1515990087-11598-16-git-send-email-nicoleotsuka@gmail.com> Message-Id: Date: Thu, 22 Feb 2018 13:16:20 +0000 Cc: alsa-devel@alsa-project.org, arnaud.mouiche@invoxia.com, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, mail@maciej.szmigiero.name, caleb@crome.org, timur@tabi.org, broonie@kernel.org, kernel@pengutronix.de, lukma@denx.de, fabio.estevam@nxp.com, linuxppc-dev@lists.ozlabs.org Subject: [alsa-devel] Applied "ASoC: fsl_ssi: Add bool synchronous to mark synchronous mode" to the asoc tree X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org The patch ASoC: fsl_ssi: Add bool synchronous to mark synchronous mode has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From badc9595bc15686be3b01e3554421647de348df0 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Mon, 12 Feb 2018 14:03:23 -0800 Subject: [PATCH] ASoC: fsl_ssi: Add bool synchronous to mark synchronous mode Using symmetric_rates in the cpu_dai_drv is a bit implicit, so this patch adds a bool synchronous instead. Signed-off-by: Nicolin Chen Tested-by: Caleb Crome Tested-by: Maciej S. Szmigiero Reviewed-by: Maciej S. Szmigiero Signed-off-by: Mark Brown --- sound/soc/fsl/fsl_ssi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.16.1 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index ed9102d91cf5..b58fabe77c6f 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -217,6 +217,7 @@ struct fsl_ssi_soc_data { * @dai_fmt: DAI configuration this device is currently used with * @streams: Mask of current active streams: BIT(TX) and BIT(RX) * @i2s_net: I2S and Network mode configurations of SCR register + * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK * @use_dma: DMA is used or FIQ with stream filter * @use_dual_fifo: DMA with support for dual FIFO mode * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree @@ -262,6 +263,7 @@ struct fsl_ssi { unsigned int dai_fmt; u8 streams; u8 i2s_net; + bool synchronous; bool use_dma; bool use_dual_fifo; bool has_ipg_clk_name; @@ -673,7 +675,6 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); struct regmap *regs = ssi->regs; - int synchronous = ssi->cpu_dai_drv.symmetric_rates, ret; u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; unsigned long clkrate, baudrate, tmprate; unsigned int slots = params_channels(hw_params); @@ -681,6 +682,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, u64 sub, savesub = 100000; unsigned int freq; bool baudclk_is_used; + int ret; /* Override slots and slot_width if being specifically set... */ if (ssi->slots) @@ -759,7 +761,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; /* STCCR is used for RX in synchronous mode */ - tx2 = tx || synchronous; + tx2 = tx || ssi->synchronous; regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); if (!baudclk_is_used) { @@ -807,7 +809,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, * that should set separate configurations for STCCR and SRCCR * despite running in the synchronous mode. */ - if (enabled && ssi->cpu_dai_drv.symmetric_rates) + if (enabled && ssi->synchronous) return 0; if (fsl_ssi_is_i2s_master(ssi)) { @@ -839,7 +841,7 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, } /* In synchronous mode, the SSI uses STCCR for capture */ - tx2 = tx || ssi->cpu_dai_drv.symmetric_rates; + tx2 = tx || ssi->synchronous; regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl); return 0; @@ -968,7 +970,7 @@ static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt) srcr = strcr; /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */ - if (ssi->cpu_dai_drv.symmetric_rates || fsl_ssi_is_ac97(ssi)) { + if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) { srcr &= ~SSI_SRCR_RXDIR; scr |= SSI_SCR_SYN; } @@ -1456,6 +1458,7 @@ static int fsl_ssi_probe(struct platform_device *pdev) if (!fsl_ssi_is_ac97(ssi)) { ssi->cpu_dai_drv.symmetric_rates = 1; ssi->cpu_dai_drv.symmetric_samplebits = 1; + ssi->synchronous = true; } ssi->cpu_dai_drv.symmetric_channels = 1;