From patchwork Mon Feb 19 16:57:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 128825 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3718903ljc; Mon, 19 Feb 2018 08:57:56 -0800 (PST) X-Google-Smtp-Source: AH8x226xBrfMpoXIoIw4z/x/nq3jRaPF6VRy7MR3sOyRz4BONlihjOI/1cMxMoQGyxIk+hhy9y0j X-Received: by 10.223.176.228 with SMTP id j33mr7193151wra.67.1519059476374; Mon, 19 Feb 2018 08:57:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519059476; cv=none; d=google.com; s=arc-20160816; b=PVFdHzB5wgZZBjJ2g7X6PUDnn5jCwy72G8CClG/t1vG44+yzTiasg/eUw/ftXN7bGS nfa8jTzEPv0gbAlSVmVT/Zi8zDCYQk2T8b40W6ZqhmYJGdiINC2xnucxXoKZW+tzddvp WR2qZ2bXkfJ9yel4esGUgSMPYgNxvJ53fRdXiEDlRgsfw77idbFcAOxA4zyupIQeVm5s m/nNfZlxXE9kpNXGJmksYBuVdiYg+SIkFYPBPGNcUcOECobFBEqi+uhFkVwfLfDkrQc5 8pPYsT/DZbXNqcFON01Fur9njsEjSaaMCkHOEmx8+eQmui8omSGWuHDKA8cIyPlUWDE7 pmGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:date:message-id:in-reply-to:to:from :dkim-signature:delivered-to:arc-authentication-results; bh=sFL7d9LDpP7WKiJHN71WUtBmO2rNAmG4oAfoK0Onx6U=; b=xdJjaLSxTNIfhTkQgdbJLPivfl5PRjBNuVHi8f7oI1FhN/eDy9528U7xDxXqtyq0VK pXljpLoHAP9d3MwKcTTJ5yhFN57QyNt3B/R47avt5ggyqm+DDby9+gi3mktKQ2b9xnj9 KDbs1Ws3Bqzoi8yXal3jbrPUJ/AmDXBMNoHGEyl1EJjZ80UHbMFoX8fWpg9l/sVSIO8w 0W5qR8hGFt+6NW8L8kYIMFCWj5/Da23Y9KGTadN10Od2cdo6zr/fcV5gO2J8qKoqtpAg ZR9oW4c9KxPZzZNBvUbVF/SrQCEP+0zxvuTbozlp1umyMkIqChjgPwFZOU1bDckywlaq Yt1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=P9W9fmGQ; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Return-Path: Received: from alsa0.perex.cz (alsa0.perex.cz. [77.48.224.243]) by mx.google.com with ESMTP id f17si17856757wrg.365.2018.02.19.08.57.46; Mon, 19 Feb 2018 08:57:56 -0800 (PST) Received-SPF: pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) client-ip=77.48.224.243; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=P9W9fmGQ; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 06EEE26748A; Mon, 19 Feb 2018 17:57:45 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id EF968267439; Mon, 19 Feb 2018 17:57:37 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, SPF_PASS, T_RP_MATCHES_RCVD autolearn=disabled version=3.4.0 Received: from heliosphere.sirena.org.uk (heliosphere.sirena.org.uk [172.104.155.198]) by alsa0.perex.cz (Postfix) with ESMTP id D09D3267440 for ; Mon, 19 Feb 2018 17:57:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=WCGIURl8fd2ff4Iq2aaR3Wc+RoBXgABZMq8cG1S+lpA=; b=P9W9fmGQdt5T 37wHqMgAGlWxy2yOvshdCrQxQlgOuLu/0Eh6svpxJaAciFI/kr3XPgigq57jXteyoBosIlxiHojAv mtGuCyjiSwEcKtktsKerqb+eqOwSg0hqSx19yZRQtRWNieUHGgK43wkJ9nEPJQgBRq54Lj+JRQh+P huCHA=; Received: from debutante.sirena.org.uk ([2001:470:1f1d:6b5::3] helo=debutante) by heliosphere.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1enokr-0003sG-Gl; Mon, 19 Feb 2018 16:57:29 +0000 Received: from broonie by debutante with local (Exim 4.90_1) (envelope-from ) id 1enokr-0002FK-1c; Mon, 19 Feb 2018 16:57:29 +0000 From: Mark Brown To: Mukunda@sirena.org.uk, Vijendar In-Reply-To: <1518766434-7911-3-git-send-email-Vijendar.Mukunda@amd.com> Message-Id: Date: Mon, 19 Feb 2018 16:57:29 +0000 Cc: alsa-devel@alsa-project.org, tiwai@suse.de, lgirdwood@gmail.com, broonie@kernel.org, Vijendar Mukunda , Alexander.Deucher@amd.com Subject: [alsa-devel] Applied "ASoC: amd: Coding style changes for acp dma driver" to the asoc tree X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org The patch ASoC: amd: Coding style changes for acp dma driver has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 4376a86caa5f7011969801f41c4c2230c1685c23 Mon Sep 17 00:00:00 2001 From: "Mukunda, Vijendar" Date: Fri, 16 Feb 2018 13:03:47 +0530 Subject: [PATCH] ASoC: amd: Coding style changes for acp dma driver Removed hardcoding in dma descriptor programming api's. These changes are required to extend the logic to support dma descriptor programming for multiple i2s controller instances. Signed-off-by: Vijendar Mukunda Reviewed-by: Alex Deucher Signed-off-by: Mark Brown --- sound/soc/amd/acp-pcm-dma.c | 124 ++++++++++++++++++++++---------------------- 1 file changed, 61 insertions(+), 63 deletions(-) -- 2.16.1 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index 3c39a0d8125d..935c8fd42a7a 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -182,19 +182,18 @@ static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, * system memory <-> ACP SRAM */ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, - u32 size, int direction, - u32 pte_offset, u32 asic_type) + u32 size, int direction, u32 pte_offset, + u16 ch, u32 sram_bank, + u16 dma_dscr_idx, u32 asic_type) { u16 i; - u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { dmadscr[i].xfer_val = 0; if (direction == SNDRV_PCM_STREAM_PLAYBACK) { - dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i; - dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS - + (i * (size/2)); + dma_dscr_idx = dma_dscr_idx + i; + dmadscr[i].dest = sram_bank + (i * (size/2)); dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + (pte_offset * SZ_4K) + (i * (size/2)); switch (asic_type) { @@ -209,25 +208,19 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, (size / 2); } } else { - dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i; + dma_dscr_idx = dma_dscr_idx + i; + dmadscr[i].src = sram_bank + (i * (size/2)); + dmadscr[i].dest = + ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + + (pte_offset * SZ_4K) + (i * (size/2)); switch (asic_type) { case CHIP_STONEY: - dmadscr[i].src = ACP_SHARED_RAM_BANK_3_ADDRESS + - (i * (size/2)); - dmadscr[i].dest = - ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + - (pte_offset * SZ_4K) + (i * (size/2)); dmadscr[i].xfer_val |= BIT(22) | (ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC << 16) | (size / 2); break; default: - dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS + - (i * (size/2)); - dmadscr[i].dest = - ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + - (pte_offset * SZ_4K) + (i * (size/2)); dmadscr[i].xfer_val |= BIT(22) | (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) | @@ -237,72 +230,49 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, &dmadscr[i]); } - if (direction == SNDRV_PCM_STREAM_PLAYBACK) - config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, - PLAYBACK_START_DMA_DESCR_CH12, - NUM_DSCRS_PER_CHANNEL, - ACP_DMA_PRIORITY_LEVEL_NORMAL); - else - config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, - CAPTURE_START_DMA_DESCR_CH14, - NUM_DSCRS_PER_CHANNEL, - ACP_DMA_PRIORITY_LEVEL_NORMAL); + config_acp_dma_channel(acp_mmio, ch, + dma_dscr_idx - 1, + NUM_DSCRS_PER_CHANNEL, + ACP_DMA_PRIORITY_LEVEL_NORMAL); } /* Initialize the DMA descriptor information for transfer between * ACP SRAM <-> I2S */ -static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, - u32 size, int direction, - u32 asic_type) +static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, + int direction, u32 sram_bank, + u16 destination, u16 ch, + u16 dma_dscr_idx, u32 asic_type) { u16 i; - u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { dmadscr[i].xfer_val = 0; if (direction == SNDRV_PCM_STREAM_PLAYBACK) { - dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i; - dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS + - (i * (size/2)); + dma_dscr_idx = dma_dscr_idx + i; + dmadscr[i].src = sram_bank + (i * (size/2)); /* dmadscr[i].dest is unused by hardware. */ dmadscr[i].dest = 0; - dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) | + dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | (size / 2); } else { - dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i; + dma_dscr_idx = dma_dscr_idx + i; /* dmadscr[i].src is unused by hardware. */ dmadscr[i].src = 0; - switch (asic_type) { - case CHIP_STONEY: - dmadscr[i].dest = - ACP_SHARED_RAM_BANK_3_ADDRESS + - (i * (size / 2)); - break; - default: - dmadscr[i].dest = - ACP_SHARED_RAM_BANK_5_ADDRESS + - (i * (size / 2)); - } + dmadscr[i].dest = + sram_bank + (i * (size / 2)); dmadscr[i].xfer_val |= BIT(22) | - (FROM_ACP_I2S_1 << 16) | (size / 2); + (destination << 16) | (size / 2); } config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, &dmadscr[i]); } /* Configure the DMA channel with the above descriptore */ - if (direction == SNDRV_PCM_STREAM_PLAYBACK) - config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM, - PLAYBACK_START_DMA_DESCR_CH13, - NUM_DSCRS_PER_CHANNEL, - ACP_DMA_PRIORITY_LEVEL_NORMAL); - else - config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM, - CAPTURE_START_DMA_DESCR_CH15, - NUM_DSCRS_PER_CHANNEL, - ACP_DMA_PRIORITY_LEVEL_NORMAL); + config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, + NUM_DSCRS_PER_CHANNEL, + ACP_DMA_PRIORITY_LEVEL_NORMAL); } /* Create page table entries in ACP SRAM for the allocated memory */ @@ -344,23 +314,51 @@ static void config_acp_dma(void __iomem *acp_mmio, struct audio_substream_data *audio_config, u32 asic_type) { - u32 pte_offset; + u32 pte_offset, sram_bank; + u16 ch1, ch2, destination, dma_dscr_idx; - if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) + if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) { pte_offset = ACP_PLAYBACK_PTE_OFFSET; - else + ch1 = SYSRAM_TO_ACP_CH_NUM; + ch2 = ACP_TO_I2S_DMA_CH_NUM; + sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS; + destination = TO_ACP_I2S_1; + + } else { pte_offset = ACP_CAPTURE_PTE_OFFSET; + ch1 = SYSRAM_TO_ACP_CH_NUM; + ch2 = ACP_TO_I2S_DMA_CH_NUM; + switch (asic_type) { + case CHIP_STONEY: + sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS; + break; + default: + sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS; + } + destination = FROM_ACP_I2S_1; + } acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages, pte_offset); + if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) + dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; + else + dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14; /* Configure System memory <-> ACP SRAM DMA descriptors */ set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size, - audio_config->direction, pte_offset, asic_type); + audio_config->direction, pte_offset, + ch1, sram_bank, dma_dscr_idx, asic_type); + if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) + dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; + else + dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15; /* Configure ACP SRAM <-> I2S DMA descriptors */ set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size, - audio_config->direction, asic_type); + audio_config->direction, sram_bank, + destination, ch2, dma_dscr_idx, + asic_type); } /* Start a given DMA channel transfer */