From patchwork Tue Jun 14 15:08:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 104863 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp2100537qgf; Tue, 14 Jun 2016 08:11:07 -0700 (PDT) X-Received: by 10.194.104.196 with SMTP id gg4mr7864743wjb.112.1465917067849; Tue, 14 Jun 2016 08:11:07 -0700 (PDT) Return-Path: Received: from alsa0.perex.cz (alsa0.perex.cz. [77.48.224.243]) by mx.google.com with ESMTP id qd5si19881957wjb.196.2016.06.14.08.11.07; Tue, 14 Jun 2016 08:11:07 -0700 (PDT) Received-SPF: neutral (google.com: 77.48.224.243 is neither permitted nor denied by best guess record for domain of alsa-devel-bounces@alsa-project.org) client-ip=77.48.224.243; Authentication-Results: mx.google.com; spf=neutral (google.com: 77.48.224.243 is neither permitted nor denied by best guess record for domain of alsa-devel-bounces@alsa-project.org) smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id B63A4266A5D; Tue, 14 Jun 2016 17:11:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.2.4 (2008-01-01) on mail1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=disabled version=3.2.4 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 81CD82667DA; Tue, 14 Jun 2016 17:09:24 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 2BF252667CF; Tue, 14 Jun 2016 17:09:23 +0200 (CEST) Received: from mezzanine.sirena.org.uk (mezzanine.sirena.org.uk [106.187.55.193]) by alsa0.perex.cz (Postfix) with ESMTP id 888F0261691 for ; Tue, 14 Jun 2016 17:09:12 +0200 (CEST) Received: from [81.128.185.34] (helo=finisterre) by mezzanine.sirena.org.uk with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.84_2) (envelope-from ) id 1bCpxi-0002hq-Ly; Tue, 14 Jun 2016 15:09:07 +0000 Received: from broonie by finisterre with local (Exim 4.87) (envelope-from ) id 1bCpxb-0001RL-56; Tue, 14 Jun 2016 16:08:59 +0100 From: Mark Brown To: Jayachandran B In-Reply-To: <1465820944-14774-7-git-send-email-vinod.koul@intel.com> Message-Id: Date: Tue, 14 Jun 2016 16:08:59 +0100 X-SA-Exim-Connect-IP: 81.128.185.34 X-SA-Exim-Mail-From: broonie@sirena.org.uk X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Cc: alsa-devel@alsa-project.org, Vinod Koul , Ramesh Babu , liam.r.girdwood@linux.intel.com, patches.audio@intel.com, broonie@kernel.org Subject: [alsa-devel] Applied "ASoC: Intel: Skylake: Update DSP stall bits" to the asoc tree X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org The patch ASoC: Intel: Skylake: Update DSP stall bits has been applied to the asoc tree at git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 2f74053bead3f47ddee219f521562db941ce0ae1 Mon Sep 17 00:00:00 2001 From: Jayachandran B Date: Mon, 13 Jun 2016 17:59:03 +0530 Subject: [PATCH] ASoC: Intel: Skylake: Update DSP stall bits The stall bits needs to comprehend the number of DSP cores running, so update the stall and unstall register writes to comprehend SKL_DSP_CORES_MASK values as well. Signed-off-by: Jayachandran B Signed-off-by: Ramesh Babu Signed-off-by: Vinod Koul Signed-off-by: Mark Brown --- sound/soc/intel/skylake/skl-sst-dsp.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) -- 2.8.1 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel diff --git a/sound/soc/intel/skylake/skl-sst-dsp.c b/sound/soc/intel/skylake/skl-sst-dsp.c index 37b1d24a9a9d..33c45aa53532 100644 --- a/sound/soc/intel/skylake/skl-sst-dsp.c +++ b/sound/soc/intel/skylake/skl-sst-dsp.c @@ -106,9 +106,9 @@ static bool is_skl_dsp_core_enable(struct sst_dsp *ctx) static int skl_dsp_reset_core(struct sst_dsp *ctx) { /* stall core */ - sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_ADSPCS, - sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & - SKL_ADSPCS_CSTALL(SKL_DSP_CORES_MASK)); + sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, + SKL_ADSPCS_CSTALL_MASK, + SKL_ADSPCS_CSTALL(SKL_DSP_CORES_MASK)); /* set reset state */ return skl_dsp_core_set_reset_state(ctx); @@ -127,9 +127,8 @@ int skl_dsp_start_core(struct sst_dsp *ctx) /* run core */ dev_dbg(ctx->dev, "run core...\n"); - sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_ADSPCS, - sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & - ~SKL_ADSPCS_CSTALL(SKL_DSP_CORES_MASK)); + sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, + SKL_ADSPCS_CSTALL_MASK, 0); if (!is_skl_dsp_core_enable(ctx)) { skl_dsp_reset_core(ctx);