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[68.55.107.1]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c5b9348308sm680685485a.89.2025.03.25.14.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Mar 2025 14:18:12 -0700 (PDT) From: Brady Norander To: Mark Brown , linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org Cc: Jaroslav Kysela , Takashi Iwai , u.kleine-koenig@baylibre.com, Wu Bo , Brady Norander Subject: [PATCH 3/3] ASoC: dwc: always enable/disable i2s irqs Date: Tue, 25 Mar 2025 17:18:05 -0400 Message-ID: <20250325211805.2099278-1-bradynorander@gmail.com> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 X-MailFrom: bradynorander@gmail.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: ZU4GXR747LM5ZXNPIR3KSJ2XJHIQCBJ4 X-Message-ID-Hash: ZU4GXR747LM5ZXNPIR3KSJ2XJHIQCBJ4 X-Mailman-Approved-At: Wed, 26 Mar 2025 09:11:31 +0000 X-Mailman-Version: 3.3.9 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Commit a42e988 ("ASoC: dwc: add DMA handshake control") changed the behavior of the driver to not enable or disable i2s irqs if using DMA. This breaks platforms such as AMD ACP. Revert to the old behavior by always enabling and disabling i2s irqs while keeping DMA handshake control. Fixes: a42e988 ("ASoC: dwc: add DMA handshake control") Signed-off-by: Brady Norander --- sound/soc/dwc/dwc-i2s.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c index 57b789d7fbed..5b4f20dbf7bb 100644 --- a/sound/soc/dwc/dwc-i2s.c +++ b/sound/soc/dwc/dwc-i2s.c @@ -199,12 +199,10 @@ static void i2s_start(struct dw_i2s_dev *dev, else i2s_write_reg(dev->i2s_base, IRER, 1); - /* I2S needs to enable IRQ to make a handshake with DMAC on the JH7110 SoC */ - if (dev->use_pio || dev->is_jh7110) - i2s_enable_irqs(dev, substream->stream, config->chan_nr); - else + if (!(dev->use_pio || dev->is_jh7110)) i2s_enable_dma(dev, substream->stream); + i2s_enable_irqs(dev, substream->stream, config->chan_nr); i2s_write_reg(dev->i2s_base, CER, 1); } @@ -218,11 +216,12 @@ static void i2s_stop(struct dw_i2s_dev *dev, else i2s_write_reg(dev->i2s_base, IRER, 0); - if (dev->use_pio || dev->is_jh7110) - i2s_disable_irqs(dev, substream->stream, 8); - else + if (!(dev->use_pio || dev->is_jh7110)) i2s_disable_dma(dev, substream->stream); + i2s_disable_irqs(dev, substream->stream, 8); + + if (!dev->active) { i2s_write_reg(dev->i2s_base, CER, 0); i2s_write_reg(dev->i2s_base, IER, 0);