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Tue, 13 Aug 2024 06:00:16 -0500 From: Vijendar Mukunda To: CC: , , , , , , , , , , , , , , , , Vijendar Mukunda Subject: [PATCH V2 1/2] ASoC: SOF: amd: move iram-dram fence register programming sequence Date: Tue, 13 Aug 2024 16:29:43 +0530 Message-ID: <20240813105944.3126903-1-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F2:EE_|CH3PR12MB9148:EE_ X-MS-Office365-Filtering-Correlation-Id: 8829dd5c-66f8-4baa-2528-08dcbb8720aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: AUtM4IUZupazWFPGa9d7W1YHFtREpwyQnMfsiADF73F+y2UkwrxyImfDTZEJvpnnzkGlyrweXl2w7N3QlF+Bvi56KdkfXW9VHeK4y7c3cosUdHrJH4g7JsZgukqV/8yZocCnFVFSlfcfbIJBcyO3FpeJHBynK/CCg41uHTRhlzFoHEakRyjGpBdA20HxlPBfyu1okWEdr6r+Eak0IkiTzilEg8CRNJLqzxQBn46Fl8IVbN/fl9Ls690MMMcMK3PmzF0xq2qGqQI7yIQsOaiWYlSTNlEa2dIYZ517/OgMvA2FUZPsa0+L5UKuJ8/ZQXATTClyQnok5TeppQZxtOow4PdprXJZi3WjAiiCG/PAgB0CY7U/3Hb7kyXFzrs2CdVJE0t2bEejusDrtlfbPd7kQ5HJsvknzhAPnKL4cVmUWBXb1XzWk7zyZPob3b4JKhrFhwEPIBd/sN4552baSNb2ovXKkJ6mxM4ccPgN0efFIzo878snMUXho2ycYWCZfPtaPGcrD0BgrorgyIeTwaGDM6+R64DqnpRY0kQ54ZK6+NkivzKLxtVp5gnumK8l1Bb8Hga3TcNo/pB0TJVAPzyw45frlT5825XXDnaCnhncqyKDSRJiEfBXRz20u6wt/XL+iIJpMfiEMxhNTi/eD4YEDbVKd6o0e32WPvwHafb6m8+JH8HpOpPFmYV9J5B2dMwstggRrvx3A+Y6UDVqQRSHmIBXHnOPDooLBZ0+5HpsQ8Knp6oJCKqDRqGhUwxzKhmO8o3/zGoSY+oYx/OyGvGF8ImrW3fX6S8UuJn5BHcY7aHMkfsUC9q9xV9pDb8OoWHixvn1aVumKsD0Ve/5gTjsSVFRDz+N4nRBhWs2WCZ4NRXUi85kbib24KyGZTcTpPJ+YPCGyOT3tUCj7ea/h3nA3R4yzPIjTOs6y+RN2FB04fn7gaQg0pzjgTGDh58ME/gwUVwpmOvIFRgXQoGoNvs3m06Wxdiy3CFRfFsNrOqW0Fur/9+wpdnzmKvfVU29YEEsbRuzR62XsctrZVjw6GJxPGUJr0KzLaf5YTZV2Ey1tWbJwaYUd6j7yOicRnVpSE0kLXk/3qLXfjxZPCpQxzxXDGPABQZZ/PJCzq8uXQRFCgbxC/gqtP4qyyl3oAPZmDou3Zd3hXgC5UOikp1nH9c9/VRyIiknrUbim+6/mj10oT/I3prb97ExgjXnqo0wxTYVTilQTXKEB5mmBzj3wdDu7rrJVq39NerC7svK+CW/hHPEfZjm4YusjO4ABy2vYksYRyTssuleIikJACHbhuWJ0wtrN7fkmxtkOc/doveg1xtrgj6mY1YVjovlkR0+C1eb9+tITrHm/0o+ZyewteC8eWpYWWFuVOhkSo3oD4mIG59SNxRYgcf1DHmV0Ye0Y0pSGglGdDhufEzjWKNGQuuyP6cOufZCO/0sLhm1vkutwjBMm++ayVqDhtMR7CS2rkdK X-Forefront-Antispam-Report: CIP:165.204.84.17; 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no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.9 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: The existing code modifies IRAM and DRAM size after sha dma start for vangogh platform. The problem with this sequence is that it might cause sha dma failure when firmware code binary size is greater than the default IRAM size. To fix this issue, Move the iram-dram fence register sequence prior to sha dma start. Fixes: 094d11768f74 ("ASoC: SOF: amd: Skip IRAM/DRAM size modification for Steam Deck OLED") Signed-off-by: Vijendar Mukunda --- changes since v1: - Rephrase commit description sound/soc/sof/amd/acp.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index 7b122656efd1..b8d4f986f89d 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -263,6 +263,17 @@ int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); + + /* psp_send_cmd only required for vangogh platform (rev - 5) */ + if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { + /* Modify IRAM and DRAM size */ + ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); + if (ret) + return ret; + ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); + if (ret) + return ret; + } snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, @@ -280,17 +291,6 @@ int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, return ret; } - /* psp_send_cmd only required for vangogh platform (rev - 5) */ - if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { - /* Modify IRAM and DRAM size */ - ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); - if (ret) - return ret; - ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); - if (ret) - return ret; - } - ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);