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Mon, 12 Aug 2024 06:05:33 -0500 From: Vijendar Mukunda To: CC: , , , , , , , , , , , , , , , , Vijendar Mukunda , Daniel Baluta Subject: [PATCH 1/2] ASoC: SOF: amd: move iram-dram fence register programming sequence Date: Mon, 12 Aug 2024 16:35:09 +0530 Message-ID: <20240812110514.2683056-1-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709A:EE_|SA0PR12MB4350:EE_ X-MS-Office365-Filtering-Correlation-Id: 4396fd6f-2423-497f-813e-08dcbabeb355 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: I2BMaDkROUQLrha3uvsF1+VpclzICqKsXJOdxDzXd0y+0POcJfirQjr5rLvHMRDN0dWs2/EEL8QVqFw7DdTLOOfo9W7DFiOPHBskVEGUfcSdwKnlZpLC1H6MeqoNIi9Z1f+VG2LdN/KwCq5RjbOG/5jO6IgSDem2/zdNCs1u9TRY6JOGedpC4Rti8KfTy9nlI1BA6Ycj+PclkLOWdJRWLnXF3r322PuP4B8aPni7pWEpjOa0J6lP3JVfma19JwuJsDAgsdaIjNNXUeB9lnEdr/pcNqZn4gK4lDkTER6zx9uaneAgL6IKKEQjaacyS29cWpGbMtVYH1v9LTTUHdpmhCDAecCzG1Ma7/xCN5QbkV35wyUkxjKrtVkXNaYBWTOUJND0AcaMZSm01BsXkqlXF3ozJoCZBSzpc09YBBgRrT/inzOCTMelYCmZBjw2jehL9ekZiP77rW6/FU4etqBdfINsj96wx8uMgkovSokbzXTggAUwJ65KEeJjEch+MjNQnJ4zPsbWuAMVCYnJRZDcZA3bP6HRd7oNj+fmb9LFD0BSO5wIOS0UVXC2NX07pQLK2WShbbIrfEgIhpy//aDTMehgnA4P94AzbL5nWSSBQ+ncffVN8K3dEUJv+aZxYQ+9jNQxW8NcmI39G0iCKCCcCHl5qfQ6xFdGE4JwPwMHgMdiZu6eZeqyqdAh4aNeTT38N9kP25fByIdmunGDUnT3fD5mnLtONpD1k5mahLq76luCMyKFyj6llkniIxQLfGrnLY/hKzn8oKTw3eN/F/QVJhtmqXT9MmwifgK1AmG6f1M8PCfJgVLx3UQzvQpqFjv4oKB3HT3pnOc2Avm//zpz//e4Mw+HwO1wVvH+hML63fYr/35kjsXkwGED6loDXmSQdNMw/Xo0kjQCVqPiHsI7Wnao9qSE/RQTK1/Ypsa3CSsqmkMpY5llz/Nr8LVddFnX2EE2GZrTGGwZL0eAzxddTQKa6bu5RmvTNySnDh97r7E+fJFf9iSgH6YkXwCicP+PVhE91tCjsnOlig93blGYnv4mFP64NXR9ZnOaJTLHyLnytjGuqJrYcKCs9xj04zrgeCk7OLc3RQN63hrusNhJ7uqb0qQfSmbo5fQcfKrwM2uklUheDKWE4mPB0MR7eOTwjRtd5Ygur3/dWrgmzP40psQVL69/S3PIAaurFyEKfsQOZTgjVFYSiLnCknsDZ7JhPxSUUquork4yXDP3HckHCeKREzQn0qEzR8z71VJX4UHfAfePAEYEe+24oZz55lAYIvi69m2M+IT8aYKTQgCAe0f/VhpgO4nEMaUPOF86mQ9/uvc/Jq3IYrhi4eZKfCqn0gxyjDh6nUjZKvCYW/8QU88RYHAiYzdLS/91ORkVZD87skwUCwjWIFjD3cW/C9WguPuIj5oJB/O9hzVoHn8u8A== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.9 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: As per design, ACP iram-dram fence register sequence should be initiated before triggering SHA dma. This ensures that IRAM size will programmed correctly before initiaing SHA dma. Fixes: 094d11768f74 ("ASoC: SOF: amd: Skip IRAM/DRAM size modification for Steam Deck OLED") Signed-off-by: Vijendar Mukunda Reviewed-by: Ranjani Sridharan Reviewed-by: Pierre-Louis Bossart --- sound/soc/sof/amd/acp.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index 7b122656efd1..b8d4f986f89d 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -263,6 +263,17 @@ int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); + + /* psp_send_cmd only required for vangogh platform (rev - 5) */ + if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { + /* Modify IRAM and DRAM size */ + ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); + if (ret) + return ret; + ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); + if (ret) + return ret; + } snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, @@ -280,17 +291,6 @@ int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, return ret; } - /* psp_send_cmd only required for vangogh platform (rev - 5) */ - if (desc->rev == 5 && !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { - /* Modify IRAM and DRAM size */ - ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); - if (ret) - return ret; - ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); - if (ret) - return ret; - } - ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);