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Thu, 8 Aug 2024 11:58:16 -0500 From: Vijendar Mukunda To: CC: , , , , , , , , , , , , , , , , Vijendar Mukunda Subject: [PATCH RESEND 2/8] ASoC: SOF: amd: fix for acp error reason registers wrong offset Date: Thu, 8 Aug 2024 22:27:47 +0530 Message-ID: <20240808165753.3414464-3-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240808165753.3414464-1-Vijendar.Mukunda@amd.com> References: <20240808165753.3414464-1-Vijendar.Mukunda@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB58:EE_|LV2PR12MB6013:EE_ X-MS-Office365-Filtering-Correlation-Id: e86d17f8-a62c-4aa7-c532-08dcb7cb4fbd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: rWAr5VKk+KWbFce8IMSz+i4KwU2RGqaJrqIofG1oaJ0EvWi3Euwpq1PrJda33lGc8yyFxBw2nw53iLa8ZBtagY4aS4rk++lcOHzxWqlwbtlrrgk35NxVAtlHc7unmD7KT1MXw4GsB1bzzrM3icCQ8bkCr8a1Ao4pQPkDslmMx2WZ6fu50SZlY/V7YLQ8jLGjB9kdtuiX3Ib2GeftnQnJ0LPahNGtt3KyQYQdGbmlAZBWGNTUQ4S2ToDLyMrKWk8o+PuCAdXkqIa8enJ7vzIGAutfsvKzai6gE7QGxgmiKQ4RCNcy2RBDa9/tlTh7eP7KyqaNCZPVrZ9UAst4ugl8Nb3hAGlz9IAOt2JjHYS6uEmYL2iax3Rpz7Pgl292q6qDEGFLQuZs5Lu9JNvLz1xHork8+GK1sfq0+szjXSGolN9ETLnMY83kRkxCaMpIONATRVSwftUB//LFHesd4NxU1lGDAyhFwFmjXwj2GXNdEJgVvnsSjcb1/3doRp8cJhxUggUUiG6HNikId/LDAuPJx6jiegP1SlRANrnhwJlkkS759HD+sbrXeIEqueWv/WbO+sy0/CoFrZp7M0uf6V9I9q+j73AqqOvapszGRtjqS+VvITX3z72yTn56TPGDCsefPS1kE6G6tzVoQO5GJ1QWTFDxUNWjSig8I6c8XRHRmrkOO0Ep+N1EQQUi6jYbfZVr8rkhHQDS3wDbBV9+ap+kgUZzHRqtcHPm39D2OtIw2I1T/g2qo88pMZQY0+hUdQeCrYwnJ1nGnL2eYe8W7SxDThoLk9NP7rSH1IPkZPyBudSmo/friakchdwYvaVuGWzvg2Bw5pA6V0vVXgGZebOmxZ+SfsbEIpk2AM0XoG9/hvuTOuV105gvk0izEFdk55Y4RyNQcwUIVvNcbs/+sj/bOH5D5K2QKZNiFC2i/G7SfoGtYIW2hJIZLc6SEHiJ+Dycohb5yow44XcXZZJM04oV183MsUN7TMDQVRCzS0ZylffagoeIoLm9K+oS2qTDgMGQqccsYrIahq57pBjc6Pcs29R2tLPMJmgxo4hUXKvqlEsEIWR/NE+M4qg4DW/eGghe6xO2YKJdjsTNIAPrhK0CChZq9mpu3yGOvuKlofaOOfs6tUc+/KSPqALw3gG1oUwdccpBtSDFoGa67t3ea5f0l6irl2ggs03ITEHOH5QpTHIt+rAFFT9CIOCnqPT7qS/7XRQ6Kq71asyLAeC7S9sXWgA2JJKhhHrfO31hJy/bfQlstUbCFk7K1oRCkzCfPFEH04HZIcseZYsvGMnhlqYMFVv63XxTZeq0QSw5p6geFj0gL4y0hZmkpCB5wTVTBNcRpjgrURDt2/91vuEAcLKC4h20IOY21HaExNaVe9GOzAzucZIx9LtKNStdVhkUnU/aoI03Zq5BppW9vk+gyx9JzrPtdZl5c9HscMk+Jd0uUTDG2YpnxmwXtwf6PohHtnVx X-Forefront-Antispam-Report: CIP:165.204.84.17; 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no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.9 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Fix the incorrect register offsets for acp error reason registers. Add 'acp_sw0_i2s_err_reason' as register field in acp descriptor structure and update the value based on the acp variant. ACP_SW1_ERROR_REASON register was added from Rembrandt platform onwards. Add conditional check for the same. Fixes: 96eb81851012 ("ASoC: SOF: amd: add interrupt handling for SoundWire manager devices") Signed-off-by: Vijendar Mukunda Reviewed-by: Ranjani Sridharan Reviewed-by: Pierre-Louis Bossart --- sound/soc/sof/amd/acp-dsp-offset.h | 3 ++- sound/soc/sof/amd/acp.c | 5 +++-- sound/soc/sof/amd/acp.h | 1 + sound/soc/sof/amd/pci-acp63.c | 1 + sound/soc/sof/amd/pci-rmb.c | 1 + sound/soc/sof/amd/pci-rn.c | 1 + 6 files changed, 9 insertions(+), 3 deletions(-) diff --git a/sound/soc/sof/amd/acp-dsp-offset.h b/sound/soc/sof/amd/acp-dsp-offset.h index 66968efda869..072b703f9b3f 100644 --- a/sound/soc/sof/amd/acp-dsp-offset.h +++ b/sound/soc/sof/amd/acp-dsp-offset.h @@ -83,7 +83,8 @@ #define ACP6X_AXI2DAGB_SEM_0 0x1874 /* ACP common registers to report errors related to I2S & SoundWire interfaces */ -#define ACP_SW0_I2S_ERROR_REASON 0x18B4 +#define ACP3X_SW_I2S_ERROR_REASON 0x18C8 +#define ACP6X_SW0_I2S_ERROR_REASON 0x18B4 #define ACP_SW1_I2S_ERROR_REASON 0x1A50 /* Registers from ACP_SHA block */ diff --git a/sound/soc/sof/amd/acp.c b/sound/soc/sof/amd/acp.c index d0b7d1c54248..9ce8b5ccb3d7 100644 --- a/sound/soc/sof/amd/acp.c +++ b/sound/soc/sof/amd/acp.c @@ -403,8 +403,9 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_id) if (val & ACP_ERROR_IRQ_MASK) { snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); - snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0); - snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0); + snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); + if (adata->pci_rev >= ACP_RMB_PCI_ID) + snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); irq_flag = 1; } diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 6ac853ff6093..f6f0fcfeb691 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -204,6 +204,7 @@ struct sof_amd_acp_desc { u32 reg_start_addr; u32 reg_end_addr; u32 acp_error_stat; + u32 acp_sw0_i2s_err_reason; u32 sdw_max_link_count; u64 sdw_acpi_dev_addr; }; diff --git a/sound/soc/sof/amd/pci-acp63.c b/sound/soc/sof/amd/pci-acp63.c index c3da70549995..e90658ba2bd7 100644 --- a/sound/soc/sof/amd/pci-acp63.c +++ b/sound/soc/sof/amd/pci-acp63.c @@ -36,6 +36,7 @@ static const struct sof_amd_acp_desc acp63_chip_info = { .ext_intr_stat = ACP6X_EXT_INTR_STAT, .ext_intr_stat1 = ACP6X_EXT_INTR_STAT1, .acp_error_stat = ACP6X_ERROR_STATUS, + .acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON, .dsp_intr_base = ACP6X_DSP_SW_INTR_BASE, .sram_pte_offset = ACP6X_SRAM_PTE_OFFSET, .hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0, diff --git a/sound/soc/sof/amd/pci-rmb.c b/sound/soc/sof/amd/pci-rmb.c index 194b7ff37e9e..a366f904e6f3 100644 --- a/sound/soc/sof/amd/pci-rmb.c +++ b/sound/soc/sof/amd/pci-rmb.c @@ -34,6 +34,7 @@ static const struct sof_amd_acp_desc rembrandt_chip_info = { .ext_intr_stat = ACP6X_EXT_INTR_STAT, .dsp_intr_base = ACP6X_DSP_SW_INTR_BASE, .acp_error_stat = ACP6X_ERROR_STATUS, + .acp_sw0_i2s_err_reason = ACP6X_SW0_I2S_ERROR_REASON, .sram_pte_offset = ACP6X_SRAM_PTE_OFFSET, .hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0, .fusion_dsp_offset = ACP6X_DSP_FUSION_RUNSTALL, diff --git a/sound/soc/sof/amd/pci-rn.c b/sound/soc/sof/amd/pci-rn.c index bff2d979ea6a..2b7c53470ce8 100644 --- a/sound/soc/sof/amd/pci-rn.c +++ b/sound/soc/sof/amd/pci-rn.c @@ -34,6 +34,7 @@ static const struct sof_amd_acp_desc renoir_chip_info = { .ext_intr_stat = ACP3X_EXT_INTR_STAT, .dsp_intr_base = ACP3X_DSP_SW_INTR_BASE, .acp_error_stat = ACP3X_ERROR_STATUS, + .acp_sw0_i2s_err_reason = ACP3X_SW_I2S_ERROR_REASON, .sram_pte_offset = ACP3X_SRAM_PTE_OFFSET, .hw_semaphore_offset = ACP3X_AXI2DAGB_SEM_0, .acp_clkmux_sel = ACP3X_CLKMUX_SEL,