| Message ID | 20230623203056.689705-27-varshini.rajendran@microchip.com |
|---|---|
| State | Accepted |
| Commit | 577293d391da30427fa193e7c4b290db1b0b9a3a |
| Headers | show
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23 Jun 2023 13:44:21 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:44:07 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:43:38 -0700 From: Varshini Rajendran <varshini.rajendran@microchip.com> To: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>, <claudiu.beznea@microchip.com>, <mturquette@baylibre.com>, <sboyd@kernel.org>, <herbert@gondor.apana.org.au>, <davem@davemloft.net>, <vkoul@kernel.org>, <tglx@linutronix.de>, <maz@kernel.org>, <lee@kernel.org>, <ulf.hansson@linaro.org>, <tudor.ambarus@linaro.org>, <miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>, <edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>, <linus.walleij@linaro.org>, <p.zabel@pengutronix.de>, <olivia@selenic.com>, <a.zummo@towertech.it>, <radu_nicolae.pirea@upb.ro>, <richard.genoud@gmail.com>, <gregkh@linuxfoundation.org>, <lgirdwood@gmail.com>, <broonie@kernel.org>, <wim@linux-watchdog.org>, <linux@roeck-us.net>, <arnd@arndb.de>, <olof@lixom.net>, <soc@kernel.org>, <linux@armlinux.org.uk>, <sre@kernel.org>, <jerry.ray@microchip.com>, <horatiu.vultur@microchip.com>, <durai.manickamkr@microchip.com>, <varshini.rajendran@microchip.com>, <andrew@lunn.ch>, <alain.volmat@foss.st.com>, <neil.armstrong@linaro.org>, <mihai.sain@microchip.com>, <eugen.hristev@collabora.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-crypto@vger.kernel.org>, <dmaengine@vger.kernel.org>, <linux-i2c@vger.kernel.org>, <linux-mmc@vger.kernel.org>, <linux-mtd@lists.infradead.org>, <netdev@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <linux-rtc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-serial@vger.kernel.org>, <alsa-devel@alsa-project.org>, <linux-usb@vger.kernel.org>, <linux-watchdog@vger.kernel.org>, <linux-pm@vger.kernel.org> CC: <Hari.PrasathGE@microchip.com>, <cristian.birsan@microchip.com>, <balamanikandan.gunasundar@microchip.com>, <manikandan.m@microchip.com>, <dharma.b@microchip.com>, <nayabbasha.sayed@microchip.com>, <balakrishnan.s@microchip.com> Subject: [PATCH v2 26/45] dt-bindings: pinctrl: at91: add bindings for SAM9X7 Date: Sat, 24 Jun 2023 02:00:37 +0530 Message-ID: <20230623203056.689705-27-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MailFrom: Varshini.Rajendran@microchip.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: MGDB5ENK5NUAPVBIBLA64ROQPT3PBT5O X-Message-ID-Hash: MGDB5ENK5NUAPVBIBLA64ROQPT3PBT5O X-Mailman-Approved-At: Mon, 26 Jun 2023 11:26:55 +0000 X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" <alsa-devel.alsa-project.org> Archived-At: <https://mailman.alsa-project.org/hyperkitty/list/alsa-devel@alsa-project.org/message/MGDB5ENK5NUAPVBIBLA64ROQPT3PBT5O/> List-Archive: <https://mailman.alsa-project.org/hyperkitty/list/alsa-devel@alsa-project.org/> List-Help: <mailto:alsa-devel-request@alsa-project.org?subject=help> List-Owner: <mailto:alsa-devel-owner@alsa-project.org> List-Post: <mailto:alsa-devel@alsa-project.org> List-Subscribe: <mailto:alsa-devel-join@alsa-project.org> List-Unsubscribe: <mailto:alsa-devel-leave@alsa-project.org> |
| Series |
Add support for sam9x7 SoC family
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expand
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diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index e8abbdad7b5d..5a3be10dcbfb 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt @@ -20,6 +20,7 @@ such as pull-up, multi drive, etc. Required properties for iomux controller: - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl" + or "microchip,sam9x7-pinctrl" - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be configured in this periph mode. All the periph and bank need to be describe. @@ -119,7 +120,7 @@ Some requirements for using atmel,at91rm9200-pinctrl binding: For each bank the required properties are: - compatible: "atmel,at91sam9x5-gpio" or "atmel,at91rm9200-gpio" or - "microchip,sam9x60-gpio" + "microchip,sam9x60-gpio" or "microchip,sam9x7-gpio" - reg: physical base address and length of the controller's registers - interrupts: interrupt outputs from the controller - interrupt-controller: marks the device node as an interrupt controller
Add device tree binding for SAM9X7 pin controller. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> --- .../devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)