From patchwork Fri Jun 23 20:30:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 696565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1425FEB64D7 for ; Mon, 26 Jun 2023 11:23:33 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id EAE87A4A; Mon, 26 Jun 2023 13:22:40 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz EAE87A4A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1687778611; bh=gvnR65uyKMk5CUoToEoiuPKzluNwCII060FV6LYqd6M=; h=From:To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=iQkXZMsGGYY7uHdJlNo2xYxsrkIXlTaOmg6aDiU17kLIRoIo4cn4JRRF4hTaMI/nM +H+nx9PLH11R4l6rU8JVC5n7WAIBNawTt1zpRA6CAVNhedYjWHVlUb7+QeCPWmDxH7 DTredDlnJSfXbvBAQr61KcbzFKejKradpvNn1KjI= Received: by alsa1.perex.cz (Postfix, from userid 50401) id 5A792F805ED; Mon, 26 Jun 2023 13:20:46 +0200 (CEST) Received: from mailman-core.alsa-project.org (mailman-core.alsa-project.org [10.254.200.10]) by alsa1.perex.cz (Postfix) with ESMTP id 5E1D3F805C4; Mon, 26 Jun 2023 13:20:45 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 5FB15F80141; Fri, 23 Jun 2023 22:37:55 +0200 (CEST) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 16B47F8003A for ; Fri, 23 Jun 2023 22:37:51 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 16B47F8003A Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key, unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=w+Llz4s6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687552673; x=1719088673; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gvnR65uyKMk5CUoToEoiuPKzluNwCII060FV6LYqd6M=; b=w+Llz4s6x17IzkS3/39iEQWJsWDqO8b6IeSGqKhgEgJMGeOpAGIhpuNt r5UHXnh3F2wYt3BcMPVGEci7xfy3r+NihHAXElwoWjC8DOZPRwylxcti4 alDDxJSImEkCqM3ZMD0op66ulqC+4YN2BwBq556M3ZizbThtL+J/r0xKw KlTpAT1I7DjbVYngZJwpfk5zi2GaDWF3A3YqA9JqPoKlntemPkQXW81sJ jhBFkGP8TzbyhWcHEPwuqGyuyJFkkXLtkLfc/Yg6ZrQF0vev2KmsV52mH e1KhbkEJuuP6prLCTLME8x/JIruTZErz3Sh3H2RWuyjTxBB0uenf1KwZ8 Q==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="158362329" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:37:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:37:48 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:37:21 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 13/45] dt-bindings: atmel-sysreg: add bindings for sam9x7 Date: Sat, 24 Jun 2023 02:00:24 +0530 Message-ID: <20230623203056.689705-14-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-MailFrom: Varshini.Rajendran@microchip.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: 7B26DMJD72QZ26WDHCQ5IG7MTGVA35FJ X-Message-ID-Hash: 7B26DMJD72QZ26WDHCQ5IG7MTGVA35FJ X-Mailman-Approved-At: Mon, 26 Jun 2023 11:20:29 +0000 X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Add RAM controller, shutdown controller & SFR DT bindings. Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index ab1b352344ae..1e7349987d77 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -11,7 +11,7 @@ PIT Timer required properties: shared across all System Controller members. PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" +- compatible: Should be "microchip,sam9x60-pit64b" or "microchip,sam9x7-pit64b" - reg: Should contain registers location and length - interrupts: Should contain interrupt for PIT64B timer - clocks: Should contain the available clock sources for PIT64B timer. @@ -31,6 +31,7 @@ RAMC SDRAM/DDR Controller required properties: "atmel,at91sam9g45-ddramc", "atmel,sama5d3-ddramc", "microchip,sam9x60-ddramc", + "microchip,sam9x7-ddramc", "microchip,sama7g5-uddrc" - reg: Should contain registers location and length @@ -89,7 +90,7 @@ SHDWC SAMA5D2-Compatible Shutdown Controller required properties: - compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or - "microchip,sama7g5-shdwc" + "microchip,sama7g5-shdwc" or "microchip,sam9x7-shdwc" - reg: should contain registers location and length - clocks: phandle to input clock. - #address-cells: should be one. The cell is the wake-up input index. @@ -156,7 +157,7 @@ required properties: - compatible: Should be "atmel,-sfr", "syscon" or "atmel,-sfrbu", "syscon" can be "sama5d3", "sama5d4" or "sama5d2". - It also can be "microchip,sam9x60-sfr", "syscon". + It also can be "microchip,sam9x60-sfr" or "microchip,sam9x7-sfr", "syscon". - reg: Should contain registers location and length sfr@f0038000 {