From patchwork Thu Sep 22 21:36:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ranjani Sridharan X-Patchwork-Id: 608266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F17EECAAD8 for ; Thu, 22 Sep 2022 21:39:40 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 75CF2210; Thu, 22 Sep 2022 23:38:48 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 75CF2210 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1663882778; bh=9+XyEwqVhuVETaOy9fDOurk+KexmZOQvdRy7z19MHD8=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=WEEcz0waASxpJJcaRKwuKPewmr8AE/jSwp5k36/GTHua3fcVGr6cg5f7Byk8/dNFv o/mgLumy8r8pEpp9htVzFH1c8D0KVeLVJqQNSl3RTmq7rIWYZ+NHTKc4cXEsq0XZ6L TCr9IgfdRfRpDjgDfUz5YhSyFIaG/e56UHSDLUGE= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 195AEF80564; Thu, 22 Sep 2022 23:37:16 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 93FE4F8054A; Thu, 22 Sep 2022 23:37:09 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 62B43F804AA for ; Thu, 22 Sep 2022 23:36:58 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 62B43F804AA Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cVrImBQT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663882619; x=1695418619; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9+XyEwqVhuVETaOy9fDOurk+KexmZOQvdRy7z19MHD8=; b=cVrImBQT3VbE/D+HweAPQXAg31mZJWkppgzeC8MTgcir49ll3MUsTj2a 2/r9e+7YPH1ZiBRU6jSzBA6VAwaQCIjyTacpPYs0+uS4yZ34VB8Bl+OUB Q/EEcMJk4hZxswl3cIKVUutPhclxfVfaOKgIU4sfRbSy7Q7G+4BPM9nxq g7Win9+FkKVpihCLvoU7K0w8+XNCqN6JDzh7ljUC4l5G+sAOtzO0cKEIY 1sU8XK4xb3Qbwy6UxkpKwL3WQbtPL4+xU4ZhXlB3Lf7igvRIdMDlR/eBL jp2gkyCFhcU+nCzbKlN++FAcJDNo1w+Kz54lq6ED9RBFEZlQFLqBXxI+5 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10478"; a="386725783" X-IronPort-AV: E=Sophos;i="5.93,337,1654585200"; d="scan'208";a="386725783" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2022 14:36:51 -0700 X-IronPort-AV: E=Sophos;i="5.93,337,1654585200"; d="scan'208";a="745550852" Received: from jpwarner-mobl2.amr.corp.intel.com (HELO rsridh2-mobl1.localdomain) ([10.254.13.62]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2022 14:36:51 -0700 From: Ranjani Sridharan To: alsa-devel@alsa-project.org Subject: [PATCH 05/10] ASoC: SOF: Intel: Add a new op for disabling interrupts Date: Thu, 22 Sep 2022 14:36:39 -0700 Message-Id: <20220922213644.666315-6-ranjani.sridharan@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922213644.666315-1-ranjani.sridharan@linux.intel.com> References: <20220922213644.666315-1-ranjani.sridharan@linux.intel.com> MIME-Version: 1.0 Cc: tiwai@suse.de, Pierre-Louis Bossart , Ranjani Sridharan , broonie@kernel.org, Rander Wang , Bard Liao X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" The sequence for disabling DSP interrupts varies between different IP versions. Signed-off-by: Ranjani Sridharan Reviewed-by: Bard Liao Reviewed-by: Rander Wang Reviewed-by: Pierre-Louis Bossart --- sound/soc/sof/intel/shim.h | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h index c7b4b1e0a824..3ceba5c39317 100644 --- a/sound/soc/sof/intel/shim.h +++ b/sound/soc/sof/intel/shim.h @@ -187,6 +187,7 @@ struct sof_intel_dsp_desc { bool (*check_sdw_irq)(struct snd_sof_dev *sdev); bool (*check_ipc_irq)(struct snd_sof_dev *sdev); int (*power_down_dsp)(struct snd_sof_dev *sdev); + int (*disable_interrupts)(struct snd_sof_dev *sdev); int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); };