From patchwork Wed Jul 27 09:08:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 594089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5890DC19F21 for ; Wed, 27 Jul 2022 09:07:27 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 7B191AE8; Wed, 27 Jul 2022 11:06:35 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 7B191AE8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1658912845; bh=NVXOybPJqEwP6MHqK15Tsb+Wcp2uLtsdOnoZ40Pv0zw=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=WO/qnQ9IClRNPLjk3djwB6Jh61e6IfmXvf+VtBn0qRuF02cH+Y1UhuI38Dzq7H3wB E1MWFx0xh8XxO7m6LFBnngUoDwh8J26iaUjY466+a8lOYV/z/RHvSkAG678L/YVgle UvWAGpJ8gZvl8WebqkyE6tg6PgNbpTFEd4inebOI= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 4263CF8015B; Wed, 27 Jul 2022 11:06:10 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 59A76F8053C; Wed, 27 Jul 2022 11:06:07 +0200 (CEST) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 30B30F800C9 for ; Wed, 27 Jul 2022 11:05:57 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 30B30F800C9 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Ez01Qda7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1658912761; x=1690448761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NVXOybPJqEwP6MHqK15Tsb+Wcp2uLtsdOnoZ40Pv0zw=; b=Ez01Qda7FJ0egSdPnPfbrIXhNRt+msH1A1TVS68sjrnzQ9+RSIMKC5gf TiMn+2R3dyX+s+RYEGrcme9EABz5ToRL+PEpnLPwioxWD50TpNTUW8Zt8 XYQSpuSlEttvFTJWw5px4Gfy+99w6L5gN+THi3e8ZP9n6Ci1hmXKazO8s nXHXK3rZC84iRxEVbW+nUMR6RAtchKnk8hkj9a+hBfORATUdrH/TuD15A d3w2ZKBP21D4Uhcb/OL0aOrOSBMGYEutertazREErwssADYzLyR5oz/dc OUGrcOfltHzH2Fofzbp183Hno0oRUZBnHcZEdpiMJVkf4R44FvN8op9p6 A==; X-IronPort-AV: E=Sophos;i="5.93,195,1654585200"; d="scan'208";a="183930488" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Jul 2022 02:05:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 27 Jul 2022 02:05:53 -0700 Received: from localhost.localdomain (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Wed, 27 Jul 2022 02:05:51 -0700 From: Claudiu Beznea To: , , , , , Subject: [PATCH v3 1/2] ASoC: mchp-spdifrx: disable end of block interrupt on failures Date: Wed, 27 Jul 2022 12:08:13 +0300 Message-ID: <20220727090814.2446111-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20220727090814.2446111-1-claudiu.beznea@microchip.com> References: <20220727090814.2446111-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Disable end of block interrupt in case of wait for completion timeout or errors to undo previously enable operation (done in mchp_spdifrx_isr_blockend_en()). Otherwise we can end up with an unbalanced reference counter for this interrupt. Fixes: ef265c55c1ac ("ASoC: mchp-spdifrx: add driver for SPDIF RX") Signed-off-by: Claudiu Beznea --- sound/soc/atmel/mchp-spdifrx.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/sound/soc/atmel/mchp-spdifrx.c b/sound/soc/atmel/mchp-spdifrx.c index 85d1d92a21db..ec0705cc40fa 100644 --- a/sound/soc/atmel/mchp-spdifrx.c +++ b/sound/soc/atmel/mchp-spdifrx.c @@ -288,15 +288,17 @@ static void mchp_spdifrx_isr_blockend_en(struct mchp_spdifrx_dev *dev) spin_unlock_irqrestore(&dev->blockend_lock, flags); } -/* called from atomic context only */ +/* called from atomic/non-atomic context */ static void mchp_spdifrx_isr_blockend_dis(struct mchp_spdifrx_dev *dev) { - spin_lock(&dev->blockend_lock); + unsigned long flags; + + spin_lock_irqsave(&dev->blockend_lock, flags); dev->blockend_refcount--; /* don't enable BLOCKEND interrupt if it's already enabled */ if (dev->blockend_refcount == 0) regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND); - spin_unlock(&dev->blockend_lock); + spin_unlock_irqrestore(&dev->blockend_lock, flags); } static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id) @@ -575,6 +577,7 @@ static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev, if (ret <= 0) { dev_dbg(dev->dev, "user data for channel %d timeout\n", channel); + mchp_spdifrx_isr_blockend_dis(dev); return ret; }