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Thu, 26 Nov 2020 10:04:18 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 26 Nov 2020 18:04:11 +0000 Received: from audio.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.15) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 26 Nov 2020 18:04:08 +0000 From: Sameer Pujar To: , , Subject: [PATCH v6 6/6] arm64: tegra: Audio graph sound card for Jetson Nano and TX1 Date: Thu, 26 Nov 2020 23:33:43 +0530 Message-ID: <1606413823-19885-7-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606413823-19885-1-git-send-email-spujar@nvidia.com> References: <1606413823-19885-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606413858; bh=7Xf2p7q6sLj/nHibZUjeyNnHhKjOwsiJG8GjpwoFLzg=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:Content-Type; b=jxGFlSqzjYIQNlrXmUGYGR5/+mKGJbDV7+oEmrJO+G0Chv6v0Kq6rLYdwAHYTuAfJ p/GT+2K6i6Z3ByA1ZBoR7e03XMKlL4nkGANgUrhxEzQcWg5yKa7ex3OKTMpOnioGla BYfBzbajjPpreos3oMdwr0Hi7zMIHGQXDx5HhFO7JBv5eeKW370pI48nWL43u6Gij0 zQcJmNQCXWVvxSuhZi4gPcRQqY8ExSpbUArXCrSjYL9UpdinXcf7nHBhTH/o8njKEB /jobKoRblbGTPmJdCOQ2NyK79qJQh12gU3EQ39FmKxypr8WbmlBjuPrGAJXO+1el58 yfqrgYgM3E1CA== Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, kuninori.morimoto.gx@renesas.com, Sameer Pujar , linux-kernel@vger.kernel.org, jonathanh@nvidia.com, sharadg@nvidia.com, linux-tegra@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Enable support for audio-graph based sound card on Jetson-Nano and Jetson-TX1. Depending on the platform, required I/O interfaces are enabled. * Jetson-Nano: Enable I2S3, I2S4, DMIC1 and DMIC2. * Jetson-TX1: Enable all I2S and DMIC interfaces. Signed-off-by: Sameer Pujar Reviewed-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 262 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 146 ++++++++++++ 2 files changed, 408 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 69102dc..747ab93 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -3,6 +3,7 @@ #include "tegra210-p2180.dtsi" #include "tegra210-p2597.dtsi" +#include "tegra210-audio-graph.dtsi" / { model = "NVIDIA Jetson TX1 Developer Kit"; @@ -127,4 +128,265 @@ status = "okay"; }; }; + + tegra_sound { + status = "okay"; + + compatible = "nvidia,tegra210-audio-graph-card"; + + dais = /* FE */ + <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, + <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, + <&admaif10_port>, + /* Router */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, + <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>, + <&xbar_dmic2_port>, <&xbar_dmic3_port>, + /* I/O DAP Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, + <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>; + + label = "jetson-tx1-ape"; + }; +}; + +&tegra_admaif { + status = "okay"; +}; + +&tegra_ahub { + status = "okay"; + + ports { + xbar_i2s1_port: port@a { + reg = <0xa>; + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + xbar_i2s2_port: port@b { + reg = <0xb>; + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; + }; + }; + xbar_i2s3_port: port@c { + reg = <0xc>; + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + xbar_i2s4_port: port@d { + reg = <0xd>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + xbar_i2s5_port: port@e { + reg = <0xe>; + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; + }; + }; + xbar_dmic1_port: port@f { + reg = <0xf>; + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + xbar_dmic2_port: port@10 { + reg = <0x10>; + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + xbar_dmic3_port: port@11 { + reg = <0x11>; + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; + }; + }; + }; +}; + +&tegra_i2s1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + i2s1_port: port@1 { + reg = <1>; + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_i2s2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; + }; + i2s2_port: port@1 { + reg = <1>; + i2s2_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_i2s3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + i2s3_port: port@1 { + reg = <1>; + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_i2s4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + i2s4_port: port@1 { + reg = <1>; + i2s4_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_i2s5 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; + }; + i2s5_port: port@1 { + reg = <1>; + i2s5_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_dmic1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + dmic1_port: port@1 { + reg = <1>; + dmic1_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_dmic2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + dmic2_port: port@1 { + reg = <1>; + dmic2_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_dmic3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + dmic3_port: port@1 { + reg = <1>; + dmic3_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 6a877de..0c917a1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -6,6 +6,7 @@ #include #include "tegra210.dtsi" +#include "tegra210-audio-graph.dtsi" / { model = "NVIDIA Jetson Nano Developer Kit"; @@ -870,4 +871,149 @@ vin-supply = <&vdd_5v0_sys>; }; + + tegra_sound { + status = "okay"; + + compatible = "nvidia,tegra210-audio-graph-card"; + + dais = /* FE */ + <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, + <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, + <&admaif10_port>, + /* Router */ + <&xbar_i2s3_port>, <&xbar_i2s4_port>, + <&xbar_dmic1_port>, <&xbar_dmic2_port>, + /* I/O DAP Ports */ + <&i2s3_port>, <&i2s4_port>, + <&dmic1_port>, <&dmic2_port>; + + label = "jetson-nano-ape"; + }; +}; + +&tegra_admaif { + status = "okay"; +}; + +&tegra_ahub { + status = "okay"; + + ports { + xbar_i2s3_port: port@c { + reg = <0xc>; + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + xbar_i2s4_port: port@d { + reg = <0xd>; + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + xbar_dmic1_port: port@f { + reg = <0xf>; + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + xbar_dmic2_port: port@10 { + reg = <0x10>; + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + }; +}; + +&tegra_i2s3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + i2s3_port: port@1 { + reg = <1>; + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_i2s4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + i2s4_port: port@1 { + reg = <1>; + i2s4_dap_ep: endpoint@0 { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_dmic1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic1_cif_ep: endpoint@0 { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + dmic1_port: port@1 { + reg = <1>; + dmic1_dap_ep: endpoint@0 { + /* Placeholder for external Codec */ + }; + }; + }; +}; + +&tegra_dmic2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dmic2_cif_ep: endpoint@0 { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + dmic2_port: port@1 { + reg = <1>; + dmic2_dap_ep: endpoint@0 { + /* Placeholder for external Codec */ + }; + }; + }; };