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[192.94.94.41]) by mx.google.com with ESMTPS id v67si9244949yhv.358.2013.06.24.06.42.22 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 24 Jun 2013 06:42:22 -0700 (PDT) Received-SPF: pass (google.com: domain of peter.ujfalusi@ti.com designates 192.94.94.41 as permitted sender) client-ip=192.94.94.41; Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r5ODgCrf023063; Mon, 24 Jun 2013 08:42:12 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r5ODgCT4002973; Mon, 24 Jun 2013 08:42:12 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Mon, 24 Jun 2013 08:42:12 -0500 Received: from barack.emea.dhcp.ti.com (barack.emea.dhcp.ti.com [137.167.125.74]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r5ODg7o8028079; Mon, 24 Jun 2013 08:42:11 -0500 From: Peter Ujfalusi To: Mark Brown , Liam Girdwood CC: Misael Lopez Cruz , , , Jyri Sarha , Samuel Ortiz Subject: [PATCH 2/4] MFD: twl6040: Update register bit definitions Date: Mon, 24 Jun 2013 15:42:04 +0200 Message-ID: <1372081326-6917-3-git-send-email-peter.ujfalusi@ti.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1372081326-6917-1-git-send-email-peter.ujfalusi@ti.com> References: <1372081326-6917-1-git-send-email-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQn7ar7dsBA3RYM4F+RShvrMEfjz4AsMHHpDRVU019yttWtqJxTpUUxMeIgYIzWelj3ElbUG X-Original-Sender: peter.ujfalusi@ti.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c02::235 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add define for: HSDRV, HFDAC, HFPGA and HFDRV enable bits Signed-off-by: Peter Ujfalusi CC: Samuel Ortiz --- include/linux/mfd/twl6040.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index 94ac944..7e7fbce 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -125,8 +125,15 @@ #define TWL6040_HSDACENA (1 << 0) #define TWL6040_HSDACMODE (1 << 1) +#define TWL6040_HSDRVENA (1 << 2) #define TWL6040_HSDRVMODE (1 << 3) +/* HFLCTL/R (0x14/0x16) fields */ + +#define TWL6040_HFDACENA (1 << 0) +#define TWL6040_HFPGAENA (1 << 1) +#define TWL6040_HFDRVENA (1 << 4) + /* VIBCTLL/R (0x18/0x1A) fields */ #define TWL6040_VIBENA (1 << 0)