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Tue, 1 Nov 2022 14:11:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 1 Nov 2022 14:11:39 +0800 From: Tinghan Shen To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Pierre-Louis Bossart , Liam Girdwood , Peter Ujfalusi , Bard Liao , Ranjani Sridharan , Kai Vehmanen , Daniel Baluta , Mark Brown , Jaroslav Kysela , Takashi Iwai , Tinghan Shen , Yaochun Hung Subject: [PATCH v1 0/2] Revise mt8186 ADSP clock driver Date: Tue, 1 Nov 2022 14:11:35 +0800 Message-ID: <20221101061137.25731-1-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sound-open-firmware@alsa-project.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Initialize the dependent clock sources for mt8186 ADSP and fix the enable/disable order of ADSP clocks. --- Tinghan Shen (2): dt-bindings: dsp: mediatek: Add default clock sources for mt8186 dsp ASoC: SOF: mediatek: Revise mt8186 ADSP clock driver .../bindings/dsp/mediatek,mt8186-dsp.yaml | 12 +++++-- sound/soc/sof/mediatek/mt8186/mt8186-clk.c | 35 +++++++++++++++---- sound/soc/sof/mediatek/mt8186/mt8186-clk.h | 2 ++ 3 files changed, 39 insertions(+), 10 deletions(-)