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[50.57.142.19]) by mx.google.com with ESMTPS id o20si3798314qgo.0.2014.05.23.07.57.36 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 23 May 2014 07:57:36 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wnqsx-0002CU-B7; Fri, 23 May 2014 14:55:51 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Wnqsv-0002CM-Hx for xen-devel@lists.xensource.com; Fri, 23 May 2014 14:55:49 +0000 Received: from [193.109.254.147:47787] by server-11.bemta-14.messagelabs.com id 82/6A-09902-4716F735; Fri, 23 May 2014 14:55:48 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-5.tower-27.messagelabs.com!1400856946!2113789!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 25615 invoked from network); 23 May 2014 14:55:48 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-5.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 23 May 2014 14:55:48 -0000 X-IronPort-AV: E=Sophos;i="4.98,894,1392163200"; d="scan'208";a="134374075" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 23 May 2014 14:55:46 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.3.181.6; Fri, 23 May 2014 10:55:46 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1Wnqo0-0003rs-Nu; Fri, 23 May 2014 15:50:44 +0100 Date: Fri, 23 May 2014 15:50:07 +0100 From: Stefano Stabellini X-X-Sender: sstabellini@kaball.uk.xensource.com To: Julien Grall In-Reply-To: <537E3C71.4070203@linaro.org> Message-ID: References: <1400761950-25035-9-git-send-email-stefano.stabellini@eu.citrix.com> <537E1C67.2020302@linaro.org> <537E3C71.4070203@linaro.org> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, xen-devel@lists.xensource.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: Re: [Xen-devel] [PATCH v8 09/13] xen/arm: second irq injection while the first irq is still inflight X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On Thu, 22 May 2014, Julien Grall wrote: > On 22/05/14 18:39, Stefano Stabellini wrote: > > On Thu, 22 May 2014, Julien Grall wrote: > > > > while the first one is still active. > > > > If the first irq is already pending (not active), clear > > > > GIC_IRQ_GUEST_QUEUED because the guest doesn't need a second > > > > notification.If the irq has already been EOI'ed then just clear the > > > > GICH_LR right away and move the interrupt to lr_pending so that it is > > > > going to be reinjected by gic_restore_pending_irqs on return to guest. > > > > > > > > If the target cpu is not the current cpu, then set GIC_IRQ_GUEST_QUEUED > > > > and send an SGI. The target cpu is going to be interrupted and call > > > > gic_clear_lrs, that is going to take the same actions. > > > > > > > > Do not call vgic_vcpu_inject_irq from gic_inject if > > > > evtchn_upcall_pending is set. If we remove that call, we don't need to > > > > special case evtchn_irq in vgic_vcpu_inject_irq anymore. > > > > We need to force the first injection of evtchn_irq (call > > > > gic_vcpu_inject_irq) from vgic_enable_irqs because evtchn_upcall_pending > > > > is already set by common code on vcpu creation. > > > > > > If you only need it for the first time. Why can't you call vgic_inject_irq > > > with the IRQ evtchn when the VCPU is turn on? > > > > > > This would remove every hack with this IRQ in the GIC code. > > > > In principle sounds nice, but in practice it is difficult and risks > > being racy. In vgic_vcpu_inject_irq we have: > > > > /* vcpu offline */ > > if ( test_bit(_VPF_down, &v->pause_flags) ) > > { > > spin_unlock_irqrestore(&v->arch.vgic.lock, flags); > > return; > > } > > > > So we can only inject the irq once the vcpu is properly up, that is > > certainly later than vcpu_initialise. > > If we call vcpu_vgic_inject right before vcpu_wake (the _VPF_down flags has > been cleared) we won't have any race condition. > > This can be done in both arch/arm/vpsci.c and common/domain.c (VCPUOP_up). > > It may require an arch specific function. Smth like arch_vcpu_prepare_up. The following change works: Acked-by: Julien Grall diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 33141e3..2a8456f 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -644,6 +644,8 @@ int arch_set_info_guest( else set_bit(_VPF_down, &v->pause_flags); + vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); + return 0; } diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index af5cd6c..d597f63 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1087,6 +1087,8 @@ int construct_dom0(struct domain *d) } #endif + vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); + for ( i = 1, cpu = 0; i < d->max_vcpus; i++ ) { cpu = cpumask_cycle(cpu, &cpu_online_map); diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 4869b87..2f86de1 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -404,17 +404,10 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) irq = i + (32 * n); p = irq_to_pending(v, irq); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status); - if ( irq == v->domain->arch.evtchn_irq && - vcpu_info(current, evtchn_upcall_pending) && - list_empty(&p->inflight) ) - vgic_vcpu_inject_irq(v, irq); - else { - unsigned long flags; - spin_lock_irqsave(&v->arch.vgic.lock, flags); - if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) - gic_raise_guest_irq(v, irq, p->priority); - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); - } + spin_lock_irqsave(&v->arch.vgic.lock, flags); + if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_raise_guest_irq(v, irq, p->priority); + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); if ( p->desc != NULL ) { spin_lock_irqsave(&p->desc->lock, flags);