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[50.57.142.19]) by mx.google.com with ESMTPS id cm8si20366251icc.80.2014.07.25.02.34.14 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 25 Jul 2014 02:34:15 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XAbrJ-0005jG-1a; Fri, 25 Jul 2014 09:32:13 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XAbrI-0005jB-44 for xen-devel@lists.xen.org; Fri, 25 Jul 2014 09:32:12 +0000 Received: from [193.109.254.147:47098] by server-11.bemta-14.messagelabs.com id 66/EC-14213-B1422D35; Fri, 25 Jul 2014 09:32:11 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-15.tower-27.messagelabs.com!1406280729!11747912!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 11892 invoked from network); 25 Jul 2014 09:32:10 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-15.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 25 Jul 2014 09:32:10 -0000 X-IronPort-AV: E=Sophos;i="5.01,730,1400025600"; d="scan'208";a="155604773" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 25 Jul 2014 09:32:08 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.3.181.6; Fri, 25 Jul 2014 05:32:07 -0400 Received: from drall.uk.xensource.com ([10.80.16.71]) by ukmail1.uk.xensource.com with smtp (Exim 4.69) (envelope-from ) id 1XAbrC-0002Jb-O3; Fri, 25 Jul 2014 10:32:07 +0100 Received: by drall.uk.xensource.com (sSMTP sendmail emulation); Fri, 25 Jul 2014 10:32:06 +0100 From: Ian Campbell To: Date: Fri, 25 Jul 2014 10:32:06 +0100 Message-ID: X-Mailer: git-send-email 1.7.10.4 MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH] xen: arm: Write to the correct PT when mapping the DTB on boot on arm64 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: We currently get away with this because when debug=y and earlyprintk is enabled the previous block of (conditinal) code would have set this up. Historically we mostly got away with it even without those options because the pre paging code would normally (at least on h/w we test) leave x4 set to the paddr of boot_second. This latent bug has always been present but was exposed by ca59618967fe "xen: arm: Handle 4K aligned hypervisor load address" (or one of the related patches) since now x4 is quite likely to point to boot_third not boot_second. Signed-off-by: Ian Campbell Acked-by: Julien Grall --- xen/arch/arm/arm64/head.S | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index dcb7071..43b5e72 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -428,6 +428,7 @@ paging: /* Map the DTB in the boot misc slot */ cbnz x22, 1f /* Only on boot CPU */ + ldr x4, =boot_second /* x4 := vaddr (boot_second) */ lsr x2, x21, #SECOND_SHIFT lsl x2, x2, #SECOND_SHIFT /* x2 := 2MB-aligned paddr of DTB */ mov x3, #PT_MEM /* x2 := 2MB RAM incl. DTB */