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[50.57.142.19]) by mx.google.com with ESMTPS id p10si4304421igx.56.2014.08.08.08.39.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 08 Aug 2014 08:39:27 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XFmEZ-0006Vb-82; Fri, 08 Aug 2014 15:37:35 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XFmEY-0006VT-BW for xen-devel@lists.xenproject.org; Fri, 08 Aug 2014 15:37:34 +0000 Received: from [193.109.254.147:17905] by server-5.bemta-14.messagelabs.com id 23/0B-28255-DBEE4E35; Fri, 08 Aug 2014 15:37:33 +0000 X-Env-Sender: Suravee.Suthikulpanit@amd.com X-Msg-Ref: server-8.tower-27.messagelabs.com!1407512251!14617411!1 X-Originating-IP: [207.46.163.203] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 9754 invoked from network); 8 Aug 2014 15:37:32 -0000 Received: from mail-bl2lp0203.outbound.protection.outlook.com (HELO na01-bl2-obe.outbound.protection.outlook.com) (207.46.163.203) by server-8.tower-27.messagelabs.com with AES256-SHA encrypted SMTP; 8 Aug 2014 15:37:32 -0000 Received: from CO1PR02MB048.namprd02.prod.outlook.com (10.242.163.25) by CO1PR02MB253.namprd02.prod.outlook.com (10.242.165.141) with Microsoft SMTP Server (TLS) id 15.0.995.14; Fri, 8 Aug 2014 15:37:28 +0000 Received: from BLUPR02CA038.namprd02.prod.outlook.com (25.160.23.156) by CO1PR02MB048.namprd02.prod.outlook.com (10.242.163.25) with Microsoft SMTP Server (TLS) id 15.0.995.14; Fri, 8 Aug 2014 15:37:07 +0000 Received: from BL2FFO11FD015.protection.gbl (2a01:111:f400:7c09::135) by BLUPR02CA038.outlook.office365.com (2a01:111:e400:8ad::28) with Microsoft SMTP Server (TLS) id 15.0.1005.10 via Frontend Transport; Fri, 8 Aug 2014 15:37:06 +0000 Received: from atltwp01.amd.com (165.204.84.221) by BL2FFO11FD015.mail.protection.outlook.com (10.173.160.223) with Microsoft SMTP Server id 15.0.990.10 via Frontend Transport; Fri, 8 Aug 2014 15:37:05 +0000 X-WSS-ID: 0N9ZVDR-07-6CT-02 X-M-MSG: Received: from satlvexedge02.amd.com (satlvexedge02.amd.com [10.177.96.29]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.3.1) with ESMTPS id 2CCACCAE7FE; Fri, 8 Aug 2014 10:37:02 -0500 (CDT) Received: from SATLEXDAG05.amd.com (10.181.40.11) by SATLVEXEDGE02.amd.com (10.177.96.29) with Microsoft SMTP Server (TLS) id 14.2.328.9; Fri, 8 Aug 2014 10:37:32 -0500 Received: from [127.0.0.1] (10.180.168.240) by satlexdag05.amd.com (10.181.40.11) with Microsoft SMTP Server id 14.2.328.9; Fri, 8 Aug 2014 11:37:04 -0400 Message-ID: <53E4EE93.3020607@amd.com> Date: Fri, 8 Aug 2014 10:36:51 -0500 From: Suravee Suthikulanit User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.6.0 MIME-Version: 1.0 To: =?UTF-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , "xen-devel@lists.xenproject.org" References: <1401876381-42977-1-git-send-email-roger.pau@citrix.com> <1401876381-42977-4-git-send-email-roger.pau@citrix.com> <53CE9FAC.8070008@amd.com> <53CEA1ED.1050604@citrix.com> In-Reply-To: <53CEA1ED.1050604@citrix.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:165.204.84.221; CTRY:US; IPV:NLI; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019004)(6009001)(428002)(479174003)(377454003)(164054003)(199002)(189002)(51704005)(24454002)(80316001)(19580405001)(19580395003)(74662001)(83322001)(64706001)(86362001)(74502001)(95666004)(80022001)(65956001)(31966008)(83072002)(44976005)(20776003)(4396001)(85852003)(21056001)(68736004)(512874002)(99396002)(87936001)(107046002)(54356999)(568964001)(81342001)(36756003)(33656002)(65816999)(83506001)(76176999)(77982001)(84326002)(84676001)(93886004)(101416001)(79102001)(87266999)(105586002)(106466001)(46102001)(64126003)(92566001)(97736001)(71186001)(92726001)(85306004)(81542001)(50986999)(76482001)(102836001); DIR:OUT; SFP:1102; SCL:1; SRVR:CO1PR02MB048; H:atltwp01.amd.com; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 02973C87BC Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-OriginatorOrg: amd4.onmicrosoft.com Cc: Jan Beulich , Xiantao Zhang Subject: Re: [Xen-devel] [PATCH v4 3/4] amd-iommu: disable iommu_hap_pt_share with AMD IOMMUs X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: suravee.suthikulpanit@amd.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On 7/22/2014 12:39 PM, Roger Pau Monné wrote: > On 22/07/14 19:30, Suravee Suthikulpanit wrote: >> Roger, >> >> I am not quite sure why you would disable "iommu_hap_pt_share" for AMD >> IOMMU. The current implementation assumes that the p2m can be shared. >> >> Also, I feel that simply just set iommu_hap_pt_share = 0 (while still >> having several places in the AMD iommu drivers and p2m-pt.c assuming >> that it can be shared) seems a bit messy. > > According to the comment in p2m.h, AMD IOMMU only supports bit 52 to bit > 58 in the pte to be 0, otherwise the hw generates page faults. > > If we want to support doing IO to devices behind an IOMMU from page > types different than p2m_ram_rw the p2m tables cannot be shared, because > the bits from 52 to 58 will indeed be different than 0, and will > generate page faults. > > Roger. > As you have mentioned, they cannot be shared due to the 52 and 58 bits. However, what I was trying to say is that, besides just simply set the flag to 0, we probably should remove existing logic in various places that assumes that AMD IOMMU can have share_p2m_table=1. If you are agree, the attachment is the patch that should do that. I have tested device-passthrough w/ the amd-iommu: disable iommu_hap_pt_share with AMD IOMMUs, and my patch and it is working. Acked-by Suravee Suthikulpanit Thanks, Suravee >From f28838679867fbbc3be6286556eed7f908eea559 Mon Sep 17 00:00:00 2001 From: Suravee Suthikulpanit Date: Fri, 8 Aug 2014 07:26:15 -0500 Subject: [PATCH] iommu: Removal of share_p2m_table from AMD IOMMU This patch removes existing logics which assumes iommu_hap_pt_share is enabled for AMD IOMMU. Signed-off-by Suravee Suthikulpanit Cd: Roger Pau MonnĂŠ Cc: Xiantao Zhang Cc: Jan Beulich --- NOTES: This patch depends on the "amd-iommu: disable iommu_hap_pt_share with AMD IOMMUs" patch from Roger Pau Monne . xen/arch/x86/mm/p2m-pt.c | 23 ++++++-------------- xen/drivers/passthrough/amd/iommu_map.c | 33 ----------------------------- xen/drivers/passthrough/amd/pci_amd_iommu.c | 4 ---- xen/drivers/passthrough/iommu.c | 2 +- 4 files changed, 8 insertions(+), 54 deletions(-) diff --git a/xen/arch/x86/mm/p2m-pt.c b/xen/arch/x86/mm/p2m-pt.c index 085ab6f..6bec0e9 100644 --- a/xen/arch/x86/mm/p2m-pt.c +++ b/xen/arch/x86/mm/p2m-pt.c @@ -36,7 +36,6 @@ #include #include #include -#include #include "mm-locks.h" @@ -653,22 +652,14 @@ p2m_pt_set_entry(struct p2m_domain *p2m, unsigned long gfn, mfn_t mfn, if ( iommu_enabled && need_iommu(p2m->domain) ) { - if ( iommu_hap_pt_share ) - { - if ( old_mfn && (old_mfn != mfn_x(mfn)) ) - amd_iommu_flush_pages(p2m->domain, gfn, page_order); - } + unsigned int flags = p2m_get_iommu_flags(p2mt); + + if ( flags != 0 ) + for ( i = 0; i < (1UL << page_order); i++ ) + iommu_map_page(p2m->domain, gfn+i, mfn_x(mfn)+i, flags); else - { - unsigned int flags = p2m_get_iommu_flags(p2mt); - - if ( flags != 0 ) - for ( i = 0; i < (1UL << page_order); i++ ) - iommu_map_page(p2m->domain, gfn+i, mfn_x(mfn)+i, flags); - else - for ( int i = 0; i < (1UL << page_order); i++ ) - iommu_unmap_page(p2m->domain, gfn+i); - } + for ( int i = 0; i < (1UL << page_order); i++ ) + iommu_unmap_page(p2m->domain, gfn+i); } out: diff --git a/xen/drivers/passthrough/amd/iommu_map.c b/xen/drivers/passthrough/amd/iommu_map.c index a8c60ec..2808c31 100644 --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -640,9 +640,6 @@ int amd_iommu_map_page(struct domain *d, unsigned long gfn, unsigned long mfn, BUG_ON( !hd->arch.root_table ); - if ( iommu_use_hap_pt(d) ) - return 0; - memset(pt_mfn, 0, sizeof(pt_mfn)); spin_lock(&hd->arch.mapping_lock); @@ -718,9 +715,6 @@ int amd_iommu_unmap_page(struct domain *d, unsigned long gfn) BUG_ON( !hd->arch.root_table ); - if ( iommu_use_hap_pt(d) ) - return 0; - memset(pt_mfn, 0, sizeof(pt_mfn)); spin_lock(&hd->arch.mapping_lock); @@ -777,30 +771,3 @@ int amd_iommu_reserve_domain_unity_map(struct domain *domain, } return 0; } - -/* Share p2m table with iommu. */ -void amd_iommu_share_p2m(struct domain *d) -{ - struct hvm_iommu *hd = domain_hvm_iommu(d); - struct page_info *p2m_table; - mfn_t pgd_mfn; - - ASSERT( is_hvm_domain(d) && d->arch.hvm_domain.hap_enabled ); - - if ( !iommu_use_hap_pt(d) ) - return; - - pgd_mfn = pagetable_get_mfn(p2m_get_pagetable(p2m_get_hostp2m(d))); - p2m_table = mfn_to_page(mfn_x(pgd_mfn)); - - if ( hd->arch.root_table != p2m_table ) - { - free_amd_iommu_pgtable(hd->arch.root_table); - hd->arch.root_table = p2m_table; - - /* When sharing p2m with iommu, paging mode = 4 */ - hd->arch.paging_mode = IOMMU_PAGING_MODE_LEVEL_4; - AMD_IOMMU_DEBUG("Share p2m table with iommu: p2m table = %#lx\n", - mfn_x(pgd_mfn)); - } -} diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/passthrough/amd/pci_amd_iommu.c index 0b301b3..c893dea 100644 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -453,9 +453,6 @@ static void deallocate_iommu_page_tables(struct domain *d) { struct hvm_iommu *hd = domain_hvm_iommu(d); - if ( iommu_use_hap_pt(d) ) - return; - spin_lock(&hd->arch.mapping_lock); if ( hd->arch.root_table ) { @@ -619,7 +616,6 @@ const struct iommu_ops amd_iommu_ops = { .setup_hpet_msi = amd_setup_hpet_msi, .suspend = amd_iommu_suspend, .resume = amd_iommu_resume, - .share_p2m = amd_iommu_share_p2m, .crash_shutdown = amd_iommu_suspend, .dump_p2m_table = amd_dump_p2m_table, }; diff --git a/xen/drivers/passthrough/iommu.c b/xen/drivers/passthrough/iommu.c index cc12735..5d3299a 100644 --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -332,7 +332,7 @@ void iommu_share_p2m_table(struct domain* d) { const struct iommu_ops *ops = iommu_get_ops(); - if ( iommu_enabled && is_hvm_domain(d) ) + if ( iommu_enabled && is_hvm_domain(d) && ops->share_p2m) ops->share_p2m(d); } -- 1.9.0