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[50.57.142.19]) by mx.google.com with ESMTPS id l2si1571401vcf.118.2014.03.14.07.33.57 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 14 Mar 2014 07:34:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WOT9K-0002fK-AC; Fri, 14 Mar 2014 14:31:50 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WOT9H-0002eb-Pz for xen-devel@lists.xenproject.org; Fri, 14 Mar 2014 14:31:48 +0000 Received: from [85.158.137.68:45830] by server-12.bemta-3.messagelabs.com id 59/77-14831-2D213235; Fri, 14 Mar 2014 14:31:46 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-15.tower-31.messagelabs.com!1394807505!675972!1 X-Originating-IP: [74.125.82.51] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 20930 invoked from network); 14 Mar 2014 14:31:46 -0000 Received: from mail-wg0-f51.google.com (HELO mail-wg0-f51.google.com) (74.125.82.51) by server-15.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 14 Mar 2014 14:31:46 -0000 Received: by mail-wg0-f51.google.com with SMTP id k14so2244862wgh.10 for ; Fri, 14 Mar 2014 07:31:45 -0700 (PDT) X-Received: by 10.180.101.230 with SMTP id fj6mr6337251wib.27.1394807505669; Fri, 14 Mar 2014 07:31:45 -0700 (PDT) Received: from [10.80.2.139] ([185.25.64.249]) by mx.google.com with ESMTPSA id uq2sm14329996wjc.5.2014.03.14.07.31.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 14 Mar 2014 07:31:45 -0700 (PDT) Message-ID: <532312CF.1020906@linaro.org> Date: Fri, 14 Mar 2014 14:31:43 +0000 From: Julien Grall User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20131104 Icedove/17.0.10 MIME-Version: 1.0 To: Ian Campbell References: <1393994786-17098-1-git-send-email-julien.grall@linaro.org> <1393994786-17098-4-git-send-email-julien.grall@linaro.org> <1394807086.6442.87.camel@kazak.uk.xensource.com> In-Reply-To: <1394807086.6442.87.camel@kazak.uk.xensource.com> Cc: xen-devel@lists.xenproject.org, tim@xen.org, stefano.stabellini@citrix.com Subject: Re: [Xen-devel] [PATCH v2 3/6] xen/arm32: Introduce lookup_processor_type X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Hi Ian, On 03/14/2014 02:24 PM, Ian Campbell wrote: > On Wed, 2014-03-05 at 12:46 +0800, Julien Grall wrote:@@ -545,6 +535,45 >> #endif /* !CONFIG_EARLY_PRINTK */ > > I got a reject here because currently this reads /* EARLY_PRINTK */. I > presume this patch is in your queue after your other series but that > they are actually unrelated. On that assumption I intend to resolve the > conflict and commit... Let me know if I shouldn't do that! There is no dependency between the both series. I should have rebase my series before to send it, sorry. You will find below the diff without the conflict. Regards, diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index e889596..72cda34 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -198,26 +198,16 @@ skip_bss: PRINT("- Setting up control registers -\r\n") /* Get processor specific proc info into r1 */ - mrc CP32(r0, MIDR) /* r0 := our cpu id */ - ldr r1, = __proc_info_start - add r1, r1, r10 /* r1 := paddr of table (start) */ - ldr r2, = __proc_info_end - add r2, r2, r10 /* r2 := paddr of table (end) */ -1: ldr r3, [r1, #PROCINFO_cpu_mask] - and r4, r0, r3 /* r4 := our cpu id with mask */ - ldr r3, [r1, #PROCINFO_cpu_val] /* r3 := cpu val in current proc info */ - teq r4, r3 - beq 2f /* Match => exit, or try next proc info */ - add r1, r1, #PROCINFO_sizeof - cmp r1, r2 - blo 1b + bl __lookup_processor_type + teq r1, #0 + bne 1f mov r4, r0 PRINT("- Missing processor info: ") mov r0, r4 bl putn PRINT(" -\r\n") b fail -2: +1: /* Jump to cpu_init */ ldr r1, [r1, #PROCINFO_cpu_init] /* r1 := vaddr(init func) */ @@ -545,6 +535,45 @@ putn: mov pc, lr #endif /* !EARLY_PRINTK */ +/* This provides a C-API version of __lookup_processor_type */ +GLOBAL(lookup_processor_type) + stmfd sp!, {r4, r10, lr} + mov r10, #0 /* r10 := offset between virt&phys */ + bl __lookup_processor_type + mov r0, r1 + ldmfd sp!, {r4, r10, pc} + +/* Read processor ID register (CP#15, CR0), and Look up in the linker-built + * supported processor list. Note that we can't use the absolute addresses for + * the __proc_info lists since we aren't running with the MMU on (and therefore, + * we are not in correct address space). We have to calculate the offset. + * + * r10: offset between virt&phys + * + * Returns: + * r0: CPUID + * r1: proc_info pointer + * Clobbers r2-r4 + */ +__lookup_processor_type: + mrc CP32(r0, MIDR) /* r0 := our cpu id */ + ldr r1, = __proc_info_start + add r1, r1, r10 /* r1 := paddr of table (start) */ + ldr r2, = __proc_info_end + add r2, r2, r10 /* r2 := paddr of table (end) */ +1: ldr r3, [r1, #PROCINFO_cpu_mask] + and r4, r0, r3 /* r4 := our cpu id with mask */ + ldr r3, [r1, #PROCINFO_cpu_val] /* r3 := cpu val in current proc info */ + teq r4, r3 + beq 2f /* Match => exit, or try next proc info */ + add r1, r1, #PROCINFO_sizeof + cmp r1, r2 + blo 1b + /* We failed to find the proc_info, return NULL */ + mov r1, #0 +2: + mov pc, lr + /* * Local variables: * mode: ASM