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[50.57.142.19]) by mx.google.com with ESMTPS id ge8si6481606icb.28.2014.07.30.06.56.16 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 30 Jul 2014 06:56:16 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XCUKp-0006GH-IN; Wed, 30 Jul 2014 13:54:27 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XCUKj-0006AW-Fg for xen-devel@lists.xen.org; Wed, 30 Jul 2014 13:54:21 +0000 Received: from [85.158.139.211:34553] by server-8.bemta-5.messagelabs.com id 78/4D-22440-C09F8D35; Wed, 30 Jul 2014 13:54:20 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-9.tower-206.messagelabs.com!1406728456!10888057!4 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8837 invoked from network); 30 Jul 2014 13:54:20 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-9.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 30 Jul 2014 13:54:20 -0000 X-IronPort-AV: E=Sophos;i="5.01,764,1400025600"; d="scan'208";a="157142872" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 30 Jul 2014 13:54:19 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.3.181.6; Wed, 30 Jul 2014 09:54:18 -0400 Received: from drall.uk.xensource.com ([10.80.16.71]) by ukmail1.uk.xensource.com with smtp (Exim 4.69) (envelope-from ) id 1XCUDu-0006v8-9l; Wed, 30 Jul 2014 14:47:19 +0100 Received: by drall.uk.xensource.com (sSMTP sendmail emulation); Wed, 30 Jul 2014 14:47:18 +0100 From: Ian Campbell To: Date: Wed, 30 Jul 2014 14:47:10 +0100 Message-ID: <265a2af15667d6fbf30a88ec7e5adebb818687fc.1406728037.git.ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <3ef2b68c511f3e31de409b76757b95c78b99d750.1406728037.git.ian.campbell@citrix.com> References: <3ef2b68c511f3e31de409b76757b95c78b99d750.1406728037.git.ian.campbell@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , vijay.kilari@gmail.com, stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH RFC 2/9] xen: arm: Implement variable levels in dump_pt_walk X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: This allows us to correctly dump 64-bit hypervisor addresses, which use a 4 level table. It also paves the way for boot-time selection of the number of levels to use in the p2m, which is required to support both 40-bit and 48-bit systems. To support multiple levels it is convenient to recast the page table walk as a loop over the levels instead of the current open coding. Signed-off-by: Ian Campbell --- xen/arch/arm/mm.c | 62 ++++++++++++++++++++++++++++---------------- xen/arch/arm/p2m.c | 4 ++- xen/include/asm-arm/page.h | 2 +- 3 files changed, 44 insertions(+), 24 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 0a243b0..fa6a729 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -84,10 +84,12 @@ lpae_t boot_third[LPAE_ENTRIES] __attribute__((__aligned__(4096))); */ #ifdef CONFIG_ARM_64 +#define HYP_PT_ROOT_LEVEL 0 lpae_t xen_pgtable[LPAE_ENTRIES] __attribute__((__aligned__(4096))); lpae_t xen_first[LPAE_ENTRIES] __attribute__((__aligned__(4096))); #define THIS_CPU_PGTABLE xen_pgtable #else +#define HYP_PT_ROOT_LEVEL 1 /* Per-CPU pagetable pages */ /* xen_pgtable == root of the trie (zeroeth level on 64-bit, first on 32-bit) */ static DEFINE_PER_CPU(lpae_t *, xen_pgtable); @@ -165,34 +167,50 @@ static inline void check_memory_layout_alignment_constraints(void) { #endif } -void dump_pt_walk(lpae_t *first, paddr_t addr) +void dump_pt_walk(lpae_t *root, paddr_t addr, int root_level) { - lpae_t *second = NULL, *third = NULL; + static const char *level_strs[4] = { "0TH", "1ST", "2ND", "3RD" }; + const unsigned int offsets[4] = { + zeroeth_table_offset(addr), + first_table_offset(addr), + second_table_offset(addr), + third_table_offset(addr) + }; + lpae_t pte, *mappings[4] = { 0, }; + int level; - if ( first_table_offset(addr) >= LPAE_ENTRIES ) - return; +#ifdef CONFIG_ARM_32 + BUG_ON(root_level < 1); +#endif + + mappings[root_level] = root; + + for ( level = root_level; level < 4; level++ ) + { + if ( offsets[level] > LPAE_ENTRIES ) + break; - printk("1ST[0x%x] = 0x%"PRIpaddr"\n", first_table_offset(addr), - first[first_table_offset(addr)].bits); - if ( !first[first_table_offset(addr)].walk.valid || - !first[first_table_offset(addr)].walk.table ) - goto done; + if ( !mappings[level] ) + { + printk("%s: Failed to map PT page\n", level_strs[level]); + break; + } - second = map_domain_page(first[first_table_offset(addr)].walk.base); - printk("2ND[0x%x] = 0x%"PRIpaddr"\n", second_table_offset(addr), - second[second_table_offset(addr)].bits); - if ( !second[second_table_offset(addr)].walk.valid || - !second[second_table_offset(addr)].walk.table ) - goto done; + pte = mappings[level][offsets[level]]; - third = map_domain_page(second[second_table_offset(addr)].walk.base); - printk("3RD[0x%x] = 0x%"PRIpaddr"\n", third_table_offset(addr), - third[third_table_offset(addr)].bits); + printk("%s[0x%x] = 0x%"PRIpaddr"\n", + level_strs[level], offsets[level], pte.bits); + if ( !pte.walk.valid || !pte.walk.table ) + break; -done: - if (third) unmap_domain_page(third); - if (second) unmap_domain_page(second); + mappings[level+1] = map_domain_page(pte.walk.base); + } + /* mappings[root_level] is provided by the caller */ + for ( level = root_level + 1 ; level < 4; level++ ) + { + unmap_domain_page(mappings[level]); + } } void dump_hyp_walk(vaddr_t addr) @@ -208,7 +226,7 @@ void dump_hyp_walk(vaddr_t addr) BUG_ON( (lpae_t *)(unsigned long)(ttbr - phys_offset) != pgtable ); else BUG_ON( virt_to_maddr(pgtable) != ttbr ); - dump_pt_walk(pgtable, addr); + dump_pt_walk(pgtable, addr, HYP_PT_ROOT_LEVEL); } /* Map a 4k page in a fixmap entry */ diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 61958ba..64efdce 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -11,6 +11,8 @@ #include #include +#define P2M_ROOT_LEVEL 1 + /* First level P2M is 2 consecutive pages */ #define P2M_ROOT_ORDER 1 #define P2M_ROOT_ENTRIES (LPAE_ENTRIES<root, page_to_mfn(p2m->root)); first = __map_domain_page(p2m->root); - dump_pt_walk(first, addr); + dump_pt_walk(first, addr, P2M_ROOT_LEVEL); unmap_domain_page(first); } diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 739038a..d1f8d52 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -352,7 +352,7 @@ static inline void flush_xen_data_tlb_range_va(unsigned long va, void flush_page_to_ram(unsigned long mfn); /* Print a walk of an arbitrary page table */ -void dump_pt_walk(lpae_t *table, paddr_t addr); +void dump_pt_walk(lpae_t *table, paddr_t addr, int root_level); /* Print a walk of the hypervisor's page tables for a virtual addr. */ extern void dump_hyp_walk(vaddr_t addr);