From patchwork Thu Oct 18 13:20:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 149143 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1972915lji; Thu, 18 Oct 2018 06:23:38 -0700 (PDT) X-Google-Smtp-Source: ACcGV605v1oxjEKDxDulqNd0G+UUs19yaMcGy8v+VJqnN+fURR+1V2MSu7Xj93w114D3xGA/SvSC X-Received: by 2002:a0d:cd44:: with SMTP id p65-v6mr15911402ywd.44.1539869018757; Thu, 18 Oct 2018 06:23:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539869018; cv=none; d=google.com; s=arc-20160816; b=oNKyhO/Ie6zeEQRaI0/t9H+23RGtSF4cgTBWqKqPtiDAHhsGn79JOzaRsdPqmVs5h5 7DVh2kOohtvAjv7SGyEgk4zbas/eE0IJ2pYsDAM9PGEWOfj4mLyb/a5XB+W+v98uXRR3 aZSbLSAzB26JxVI2F8/1IOKzwIy3V/h9VvOjC5FEQpiNvBug3WCjwG1lUa1bP5X4v63g 09ywG08tOMJnKfgnXp4+REYUCeaBDHhkZ3xIfvdnxUCElvSrl+353pbUeSIrKlxgYnem VnAR2py9UZhepJ/UA0PJXI05DK01AZDJKbcOEm3fJpUz+YmC7wD9kYXngkd05748zNWf hmjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=LvQ2bJiIcx+NmPrSCKsSAGEHKl0CGfcxzqy+z/9XXI0=; b=harbCZfcv5f46bUNre/qJNnkUnEJb3Gc5PO/f8F++vZokELfwLPQqwwJpjVrm2qbAo Je3xyLHihTtZ9QkWEFap3674CV7MMsNu06DsRutO+amBDQsdSaVw3r/pVmzI1NZENMv7 /I7K45F0QxnPibnGDRJtqc2kJdHk3gvQZEkcqIP1KFhrfHDEIhhdu0cnHBKn3ljR4uGQ ah0HAxV8YwaIMO1hYYbGv+50DgGBPoDDEOMkNS/se1by6R1PnW+gGc9UbbzVKJU4lSjH f1Y8WhIoVhDxlWSyy4JkdKDqMW4rIKrzfHt5m74ZY9bRDNgjQMIWPSDMWl9UVB/hGrN9 ffsQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id y65-v6si7646385ywa.11.2018.10.18.06.23.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Oct 2018 06:23:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8F0-00034f-GB; Thu, 18 Oct 2018 13:21:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1gD8Ez-00033a-7A for xen-devel@lists.xen.org; Thu, 18 Oct 2018 13:21:29 +0000 X-Inumbo-ID: eac8224a-d2d8-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id eac8224a-d2d8-11e8-a6a9-d7ebe60f679a; Thu, 18 Oct 2018 13:22:53 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 858431596; Thu, 18 Oct 2018 06:21:27 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDACE3F59C; Thu, 18 Oct 2018 06:21:26 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 18 Oct 2018 14:20:57 +0100 Message-Id: <20181018132109.31192-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181018132109.31192-1-julien.grall@arm.com> References: <20181018132109.31192-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH 10/22] xen/arm: Move SYSREG accessors in sysregs.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" System registers accessors are self-contained and should not be included everywhere in Xen. Move the accessors in sysregs.h and include the file when necessary. With that change, it is not necessary to include processor.h in time.h. Signed-off-by: Julien Grall Reviewed-by: Andrii Anisov --- xen/arch/arm/arm32/entry.S | 1 + xen/arch/arm/arm32/proc-v7.S | 1 + xen/arch/arm/gic-v3-lpi.c | 1 + xen/arch/arm/gic-v3.c | 1 + xen/include/asm-arm/arm32/processor.h | 62 ----------------------------- xen/include/asm-arm/arm32/sysregs.h | 74 +++++++++++++++++++++++++++++++++++ xen/include/asm-arm/arm64/processor.h | 25 ------------ xen/include/asm-arm/arm64/sysregs.h | 23 +++++++++++ xen/include/asm-arm/page.h | 1 + xen/include/asm-arm/percpu.h | 8 +--- xen/include/asm-arm/sysregs.h | 22 +++++++++++ xen/include/asm-arm/time.h | 2 +- 12 files changed, 126 insertions(+), 95 deletions(-) create mode 100644 xen/include/asm-arm/arm32/sysregs.h create mode 100644 xen/include/asm-arm/sysregs.h diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index f6908e3f16..0b4cd19abd 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -1,4 +1,5 @@ #include +#include #include #include #include diff --git a/xen/arch/arm/arm32/proc-v7.S b/xen/arch/arm/arm32/proc-v7.S index 2f3ff1e6c9..80a250d8e8 100644 --- a/xen/arch/arm/arm32/proc-v7.S +++ b/xen/arch/arm/arm32/proc-v7.S @@ -19,6 +19,7 @@ #include #include +#include ca15mp_init: ca7mp_init: diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index efd5cd62fb..e8c6e159ca 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -30,6 +30,7 @@ #include #include #include +#include /* * There could be a lot of LPIs on the host side, and they always go to diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index a7ce94789c..264a981bab 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -42,6 +42,7 @@ #include #include #include +#include /* Global state */ static struct { diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index fb330812af..4e679f3273 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -1,8 +1,6 @@ #ifndef __ASM_ARM_ARM32_PROCESSOR_H #define __ASM_ARM_ARM32_PROCESSOR_H -#include - #define ACTLR_CAXX_SMP (1<<6) #ifndef __ASSEMBLY__ @@ -60,66 +58,6 @@ struct cpu_user_regs #endif -/* Layout as used in assembly, with src/dest registers mixed in */ -#define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm, opc2 -#define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm -#define CP32(r, name...) __CP32(r, name) -#define CP64(r, name...) __CP64(r, name) - -/* Stringified for inline assembly */ -#define LOAD_CP32(r, name...) "mrc " __stringify(CP32(%r, name)) ";" -#define STORE_CP32(r, name...) "mcr " __stringify(CP32(%r, name)) ";" -#define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" -#define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" - -/* Issue a CP operation which takes no argument, - * uses r0 as a placeholder register. */ -#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" - -#ifndef __ASSEMBLY__ - -/* C wrappers */ -#define READ_CP32(name...) ({ \ - register uint32_t _r; \ - asm volatile(LOAD_CP32(0, name) : "=r" (_r)); \ - _r; }) - -#define WRITE_CP32(v, name...) do { \ - register uint32_t _r = (v); \ - asm volatile(STORE_CP32(0, name) : : "r" (_r)); \ -} while (0) - -#define READ_CP64(name...) ({ \ - register uint64_t _r; \ - asm volatile(LOAD_CP64(0, name) : "=r" (_r)); \ - _r; }) - -#define WRITE_CP64(v, name...) do { \ - register uint64_t _r = (v); \ - asm volatile(STORE_CP64(0, name) : : "r" (_r)); \ -} while (0) - -/* - * C wrappers for accessing system registers. - * - * Registers come in 3 types: - * - those which are always 32-bit regardless of AArch32 vs AArch64 - * (use {READ,WRITE}_SYSREG32). - * - those which are always 64-bit regardless of AArch32 vs AArch64 - * (use {READ,WRITE}_SYSREG64). - * - those which vary between AArch32 and AArch64 (use {READ,WRITE}_SYSREG). - */ -#define READ_SYSREG32(R...) READ_CP32(R) -#define WRITE_SYSREG32(V, R...) WRITE_CP32(V, R) - -#define READ_SYSREG64(R...) READ_CP64(R) -#define WRITE_SYSREG64(V, R...) WRITE_CP64(V, R) - -#define READ_SYSREG(R...) READ_SYSREG32(R) -#define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) - -#endif /* __ASSEMBLY__ */ - #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ /* * Local variables: diff --git a/xen/include/asm-arm/arm32/sysregs.h b/xen/include/asm-arm/arm32/sysregs.h new file mode 100644 index 0000000000..b25b59a557 --- /dev/null +++ b/xen/include/asm-arm/arm32/sysregs.h @@ -0,0 +1,74 @@ +#ifndef __ASM_ARM_ARM32_SYSREGS_H +#define __ASM_ARM_ARM32_SYSREGS_H + +#include + +/* Layout as used in assembly, with src/dest registers mixed in */ +#define __CP32(r, coproc, opc1, crn, crm, opc2) coproc, opc1, r, crn, crm, opc2 +#define __CP64(r1, r2, coproc, opc, crm) coproc, opc, r1, r2, crm +#define CP32(r, name...) __CP32(r, name) +#define CP64(r, name...) __CP64(r, name) + +/* Stringified for inline assembly */ +#define LOAD_CP32(r, name...) "mrc " __stringify(CP32(%r, name)) ";" +#define STORE_CP32(r, name...) "mcr " __stringify(CP32(%r, name)) ";" +#define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" +#define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" + +/* Issue a CP operation which takes no argument, + * uses r0 as a placeholder register. */ +#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" + +#ifndef __ASSEMBLY__ + +/* C wrappers */ +#define READ_CP32(name...) ({ \ + register uint32_t _r; \ + asm volatile(LOAD_CP32(0, name) : "=r" (_r)); \ + _r; }) + +#define WRITE_CP32(v, name...) do { \ + register uint32_t _r = (v); \ + asm volatile(STORE_CP32(0, name) : : "r" (_r)); \ +} while (0) + +#define READ_CP64(name...) ({ \ + register uint64_t _r; \ + asm volatile(LOAD_CP64(0, name) : "=r" (_r)); \ + _r; }) + +#define WRITE_CP64(v, name...) do { \ + register uint64_t _r = (v); \ + asm volatile(STORE_CP64(0, name) : : "r" (_r)); \ +} while (0) + +/* + * C wrappers for accessing system registers. + * + * Registers come in 3 types: + * - those which are always 32-bit regardless of AArch32 vs AArch64 + * (use {READ,WRITE}_SYSREG32). + * - those which are always 64-bit regardless of AArch32 vs AArch64 + * (use {READ,WRITE}_SYSREG64). + * - those which vary between AArch32 and AArch64 (use {READ,WRITE}_SYSREG). + */ +#define READ_SYSREG32(R...) READ_CP32(R) +#define WRITE_SYSREG32(V, R...) WRITE_CP32(V, R) + +#define READ_SYSREG64(R...) READ_CP64(R) +#define WRITE_SYSREG64(V, R...) WRITE_CP64(V, R) + +#define READ_SYSREG(R...) READ_SYSREG32(R) +#define WRITE_SYSREG(V, R...) WRITE_SYSREG32(V, R) + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARM_ARM32_SYSREGS_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index c18ab7203d..765de1b74b 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -3,8 +3,6 @@ #include -#include - #ifndef __ASSEMBLY__ /* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */ @@ -89,29 +87,6 @@ struct cpu_user_regs #undef __DECL_REG -/* Access to system registers */ - -#define READ_SYSREG32(name) ({ \ - uint32_t _r; \ - asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ - _r; }) -#define WRITE_SYSREG32(v, name) do { \ - uint32_t _r = v; \ - asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ -} while (0) - -#define WRITE_SYSREG64(v, name) do { \ - uint64_t _r = v; \ - asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ -} while (0) -#define READ_SYSREG64(name) ({ \ - uint64_t _r; \ - asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ - _r; }) - -#define READ_SYSREG(name) READ_SYSREG64(name) -#define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) - #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM64_PROCESSOR_H */ diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index f510925a2a..08585a969e 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -57,6 +57,29 @@ #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) +/* Access to system registers */ + +#define READ_SYSREG32(name) ({ \ + uint32_t _r; \ + asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ + _r; }) +#define WRITE_SYSREG32(v, name) do { \ + uint32_t _r = v; \ + asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ +} while (0) + +#define WRITE_SYSREG64(v, name) do { \ + uint64_t _r = v; \ + asm volatile("msr "__stringify(name)", %0" : : "r" (_r)); \ +} while (0) +#define READ_SYSREG64(name) ({ \ + uint64_t _r; \ + asm volatile("mrs %0, "__stringify(name) : "=r" (_r)); \ + _r; }) + +#define READ_SYSREG(name) READ_SYSREG64(name) +#define WRITE_SYSREG(v, name) WRITE_SYSREG64(v, name) + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index bcdea970ca..1a1713ce02 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -4,6 +4,7 @@ #include #include #include +#include #ifdef CONFIG_ARM_64 #define PADDR_BITS 48 diff --git a/xen/include/asm-arm/percpu.h b/xen/include/asm-arm/percpu.h index cdf64e0f77..6263e77251 100644 --- a/xen/include/asm-arm/percpu.h +++ b/xen/include/asm-arm/percpu.h @@ -4,13 +4,7 @@ #ifndef __ASSEMBLY__ #include -#if defined(CONFIG_ARM_32) -# include -#elif defined(CONFIG_ARM_64) -# include -#else -# error "unknown ARM variant" -#endif +#include extern char __per_cpu_start[], __per_cpu_data_end[]; extern unsigned long __per_cpu_offset[NR_CPUS]; diff --git a/xen/include/asm-arm/sysregs.h b/xen/include/asm-arm/sysregs.h new file mode 100644 index 0000000000..5c5c51bbcd --- /dev/null +++ b/xen/include/asm-arm/sysregs.h @@ -0,0 +1,22 @@ +#ifndef __ASM_ARM_SYSREGS_H +#define __ASM_ARM_SYSREGS_H + +#if defined(CONFIG_ARM_32) +# include +#elif defined(CONFIG_ARM_64) +# include +#else +# error "unknown ARM variant" +#endif + +#endif /* __ASM_ARM_SYSREGS_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + + diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index ea88e76304..9a7071a546 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -1,7 +1,7 @@ #ifndef __ARM_TIME_H__ #define __ARM_TIME_H__ -#include +#include #define DT_MATCH_TIMER \ DT_MATCH_COMPATIBLE("arm,armv7-timer"), \