From patchwork Wed Mar 21 03:34:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 132174 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1649617ljb; Tue, 20 Mar 2018 20:37:03 -0700 (PDT) X-Google-Smtp-Source: AG47ELtDS6qTU2ZrWy1SMt7NYWkFs3OEXmV1XUXQY12INAqcwKAbDf8ph/t4HgkyVQSLxqCq2BUa X-Received: by 10.107.232.10 with SMTP id f10mr17644547ioh.27.1521603423846; Tue, 20 Mar 2018 20:37:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521603423; cv=none; d=google.com; s=arc-20160816; b=RMnDFolvZ6kfs+lPEkngjlQWE/u6NNDA9s6KPzBT0a/a9jIwSQRlRXJXWAH18ofcB+ QkL2WZ7bWxyE6kW766QE3HWamYOnuc9SqyihwaaeJYsZlZCNWSIlFiWFXCIELv0gyGCa gcOStVbShikPv5KIq4E61I8gDL9lF3JhJvCNjqEyuKkPH43YeGlgyegnwa87n+SBhxj6 LqCiTpSsPSb2XiddBkPvawPt90fir4cDum2AAygNsOjZurKP+FnOXRp5wbJ8yyKb0vIc wYz+V4iry4hw2i9ywXK/+pkkarKmhbBkUqXIPyJZfEif4+CUOtljpGR6tkxKl/zTm2eW 88UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:message-id:date:to:from :arc-authentication-results; bh=fETK55K9snFRGjx7wgpXHldX1kIYsIzGEHDRb6BD5D0=; b=yq6qa9FjoWp2h8529uxjH3x7l+902TmAjOOTuOqfpXvmCnDqViNNuO5fegFmqA9awQ eWrztJheAzYYgxBuEaIOEccd4oSqog1X9lDIvO3jUFwqmeye1jE9tgZUwNCJR9yYb3vJ e9c/QM2LkQxsbnFgObVJxoz1Z54B+sptMbqyk4fMt9Wwa6mNbdkiqy3/zl1c5w5fpjpI RFUo0x3ml3UY+nx3X0CwJYGetU6/cXbw6Tn+QDoSnGH3Z8gOR+4wDYdZ9Cp+i0/ffAeN ljf4RRr782tuELurFRdmPGCPOeV+lIkxPRMMvnO354haiL29rjdZpApq4lexeH7N/3QP ooKA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 1-v6si2276037itj.157.2018.03.20.20.37.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Mar 2018 20:37:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eyUWT-0001hE-Ok; Wed, 21 Mar 2018 03:34:45 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eyUWS-0001h9-Vb for xen-devel@lists.xen.org; Wed, 21 Mar 2018 03:34:44 +0000 X-Inumbo-ID: dbfa12c6-2cb8-11e8-8248-2fda3a446a53 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id dbfa12c6-2cb8-11e8-8248-2fda3a446a53; Wed, 21 Mar 2018 03:35:11 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 03D7880D; Tue, 20 Mar 2018 20:34:43 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7B7F53F24A; Tue, 20 Mar 2018 20:34:41 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 21 Mar 2018 03:34:35 +0000 Message-Id: <20180321033435.28163-1-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 Subject: [Xen-devel] [PATCH] xen/arm: gic: Read unconditionally the source from the LRs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Commit 5cb00d1 "ARM: GIC: extend LR read/write functions to cover EOI and source" extended gic_lr to cover the source. The new field was only set for SGIs interrupt in the read function. However, the write function is writing the field unconditionally for virtual interrupt. This means that if the caller was combining the 2 functions (e.g to update the LR), the source need to be set to 0 by the caller. Unfortunately, gic_update_one_lr is not zeroing the structure before reading the LRs. This will lead to trigger the assert randomly. Instead of zeroing the structure in gic_update_one_lr, make sure that the source is written unconditionally on read. This is also simplifying the code to avoid an if statement in the read path. Lastly, properly update the comments in write_lr that was mistakenly speaking about the read lr path. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v2.c | 15 ++++++++------- xen/arch/arm/gic-v3.c | 13 ++++++++----- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 7dfe6fc68d..aa0fc6c1a1 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -480,11 +480,12 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) else { lr_reg->virt.eoi = (lrv & GICH_V2_LR_MAINTENANCE_IRQ); - if ( lr_reg->virq < NR_GIC_SGI ) - { - lr_reg->virt.source = (lrv >> GICH_V2_LR_CPUID_SHIFT) - & GICH_V2_LR_CPUID_MASK; - } + /* + * This is only valid for SGI, but it does not matter to always + * read it as it should be 0 by default. + */ + lr_reg->virt.source = (lrv >> GICH_V2_LR_CPUID_SHIFT) + & GICH_V2_LR_CPUID_MASK; } } @@ -512,8 +513,8 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) if ( lr_reg->virt.eoi ) lrv |= GICH_V2_LR_MAINTENANCE_IRQ; /* - * This is only valid for SGI, but it does not matter to always - * read it as it should be 0 by default. + * Source is only valid for SGIs, the caller should make sure + * the field virt.source is always 0 for non-SGI. */ ASSERT(!lr_reg->virt.source || lr_reg->virq < NR_GIC_SGI); lrv |= (uint32_t)lr_reg->virt.source << GICH_V2_LR_CPUID_SHIFT; diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 392cf91b58..cb41844af2 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1018,10 +1018,13 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) else { lr_reg->virt.eoi = (lrv & ICH_LR_MAINTENANCE_IRQ); - /* Source only exists for SGI and in GICv2 compatible mode */ - if ( lr_reg->virq < NR_GIC_SGI && - current->domain->arch.vgic.version == GIC_V2 ) + /* Source only exists in GICv2 compatible mode */ + if ( current->domain->arch.vgic.version == GIC_V2 ) { + /* + * This is only valid for SGI, but it does not matter to always + * read it as it should be 0 by default. + */ lr_reg->virt.source = (lrv >> ICH_LR_CPUID_SHIFT) & ICH_LR_CPUID_MASK; } @@ -1056,8 +1059,8 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) if ( vgic_version == GIC_V2 ) { /* - * This is only valid for SGI, but it does not matter to always - * read it as it should be 0 by default. + * Source is only valid for SGIs, the caller should make + * sure the field virt.source is always 0 for non-SGI. */ ASSERT(!lr->virt.source || lr->virq < NR_GIC_SGI); lrv |= (uint64_t)lr->virt.source << ICH_LR_CPUID_SHIFT;