From patchwork Fri Feb 23 16:47:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129473 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp816254lja; Fri, 23 Feb 2018 08:52:31 -0800 (PST) X-Google-Smtp-Source: AG47ELtCQ4O6azGuuLSbGXbGT2cQFXMwozFz+6cCl9WiveZ+gfNB1bajIg1QXUh1bJyKL3Zvtj5A X-Received: by 10.36.33.86 with SMTP id e83mr3066347ita.44.1519404751607; Fri, 23 Feb 2018 08:52:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519404751; cv=none; d=google.com; s=arc-20160816; b=g63uWsxNOET5lYYXqAwaw65sHRciJbhzj6MBGUvA031YHWY8f8I2gdg9xOEd4y7Lxp zSoyw9jAjDJkMASDS7GJcN113s8oJf+PMuXzApb4Ow5G5AIBVFofPkp6CF+4g3BktFaZ 7+EViIgoCr7wAOlQ6pOY5VJdZ3EonfHK6C4oxRMo7ZZSbYZkz9c6bjf5LlVm32049Zkn JIN9C950kWRzdezdDDFpS8IuJFrQq2Q+B3I2iYFEVEx0MldwKiyGy90dMoYqtj7HkQyO NM6hgCKO9IPHaLreo61eK9mv7u416OAGT4IOlLj0CTkJZH0Oz7COtncquMvf2L+E8228 m08Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=niodD7ufXW+Ybz4/blTZLtdngzg608mz5Zb43DUSgOE=; b=U14JVQ5gL/vL/n+NByG1Vt+s4yAKh/alKZUQceuDv7qab3kWEZmxCRhhrOCiHb/gvf gdmC8yBS51DhYO5CyvaKRW/rGGLNd9eQMYB9DKPbLLie24/JQ8O3TtyWLYVx8+qZrx7H +RCAaD5TAJ3O7mf3TFjZIDOwG3dNCdw/PUPtAKK2cYemUVXZiAz9m6S+yTyndKoOwB07 HUErbdu6xnqocW7yLJE2CCdFjDJ0h3oT0ldZlJo7FPOkO1pMVaLqC8A2zLVUga4CRmcO yzHKu1cKanvsyP3ySD23I0ytZen86xxfb5Mi2/HGssIMRYdevfRMcSu/9zoGHMXeffCj afgQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d12si1356111itj.169.2018.02.23.08.52.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 08:52:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGZ2-0005gh-DL; Fri, 23 Feb 2018 16:51:16 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epGZ1-0005ex-NK for xen-devel@lists.xen.org; Fri, 23 Feb 2018 16:51:15 +0000 X-Inumbo-ID: 99de868c-18b9-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 99de868c-18b9-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 16:50:06 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B1A615BE; Fri, 23 Feb 2018 08:48:23 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BCD23F25C; Fri, 23 Feb 2018 08:48:22 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 16:47:47 +0000 Message-Id: <20180223164753.27311-14-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223164753.27311-1-julien.grall@arm.com> References: <20180223164753.27311-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v4 13/19] xen/arm64: Kill PSCI_GET_VERSION as a variant-2 workaround X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Now that we've standardised on SMCCC v1.1 to perform the branch prediction invalidation, let's drop the previous band-aid. If vendors haven't updated their firmware to do SMCCC 1.1, they haven't updated PSCI either, so we don't loose anything. This is aligned with the Linux commit 3a0a397ff5ff. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v4: - Add Stefano's reviewed-by Changes in v3: - Add Volodymyr's reviewed-by Changes in v2: - Patch added --- xen/arch/arm/arm64/bpi.S | 25 ---------------------- xen/arch/arm/cpuerrata.c | 54 +++++++++++++++++------------------------------- 2 files changed, 19 insertions(+), 60 deletions(-) diff --git a/xen/arch/arm/arm64/bpi.S b/xen/arch/arm/arm64/bpi.S index b59e307b0f..d8743d955c 100644 --- a/xen/arch/arm/arm64/bpi.S +++ b/xen/arch/arm/arm64/bpi.S @@ -58,31 +58,6 @@ ENTRY(__bp_harden_hyp_vecs_start) .endr ENTRY(__bp_harden_hyp_vecs_end) -ENTRY(__psci_hyp_bp_inval_start) - sub sp, sp, #(8 * 18) - stp x16, x17, [sp, #(16 * 0)] - stp x14, x15, [sp, #(16 * 1)] - stp x12, x13, [sp, #(16 * 2)] - stp x10, x11, [sp, #(16 * 3)] - stp x8, x9, [sp, #(16 * 4)] - stp x6, x7, [sp, #(16 * 5)] - stp x4, x5, [sp, #(16 * 6)] - stp x2, x3, [sp, #(16 * 7)] - stp x0, x1, [sp, #(16 * 8)] - mov x0, #0x84000000 - smc #0 - ldp x16, x17, [sp, #(16 * 0)] - ldp x14, x15, [sp, #(16 * 1)] - ldp x12, x13, [sp, #(16 * 2)] - ldp x10, x11, [sp, #(16 * 3)] - ldp x8, x9, [sp, #(16 * 4)] - ldp x6, x7, [sp, #(16 * 5)] - ldp x4, x5, [sp, #(16 * 6)] - ldp x2, x3, [sp, #(16 * 7)] - ldp x0, x1, [sp, #(16 * 8)] - add sp, sp, #(8 * 18) -ENTRY(__psci_hyp_bp_inval_end) - ENTRY(__smccc_workaround_1_smc_start) sub sp, sp, #(8 * 4) stp x0, x1, [sp, #(8 * 2)] diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index dec9074422..4eb1567589 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -149,10 +149,11 @@ install_bp_hardening_vec(const struct arm_cpu_capabilities *entry, extern char __smccc_workaround_1_smc_start[], __smccc_workaround_1_smc_end[]; -static bool -check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) +static int enable_smccc_arch_workaround_1(void *data) { struct arm_smccc_res res; + static bool warned = false; + const struct arm_cpu_capabilities *entry = data; /* * Enable callbacks are called on every CPU based on the @@ -160,47 +161,30 @@ check_smccc_arch_workaround_1(const struct arm_cpu_capabilities *entry) * entry. */ if ( !entry->matches(entry) ) - return false; + return 0; if ( smccc_ver < SMCCC_VERSION(1, 1) ) - return false; + goto warn; arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); if ( res.a0 != ARM_SMCCC_SUCCESS ) - return false; - - return install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, - __smccc_workaround_1_smc_end, - "call ARM_SMCCC_ARCH_WORKAROUND_1"); -} + goto warn; -extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[]; + return !install_bp_hardening_vec(entry,__smccc_workaround_1_smc_start, + __smccc_workaround_1_smc_end, + "call ARM_SMCCC_ARCH_WORKAROUND_1"); -static int enable_psci_bp_hardening(void *data) -{ - bool ret = true; - static bool warned = false; - - if ( check_smccc_arch_workaround_1(data) ) - return 0; - /* - * The mitigation is using PSCI version function to invalidate the - * branch predictor. This function is only available with PSCI 0.2 - * and later. - */ - else if ( psci_ver >= PSCI_VERSION(0, 2) ) - ret = install_bp_hardening_vec(data, __psci_hyp_bp_inval_start, - __psci_hyp_bp_inval_end, - "call PSCI get version"); - else if ( !warned ) +warn: + if ( !warned ) { ASSERT(system_state < SYS_STATE_active); - warning_add("PSCI 0.2 or later is required for the branch predictor hardening.\n"); - warned = true; + warning_add("No support for ARM_SMCCC_ARCH_WORKAROUND_1.\n" + "Please update your firmware.\n"); + warned = false; } - return !ret; + return 0; } #endif /* CONFIG_ARM64_HARDEN_BRANCH_PREDICTOR */ @@ -316,22 +300,22 @@ static const struct arm_cpu_capabilities arm_errata[] = { { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, { .capability = ARM_HARDEN_BRANCH_PREDICTOR, MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), - .enable = enable_psci_bp_hardening, + .enable = enable_smccc_arch_workaround_1, }, #endif #ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR