Message ID | 20180131165334.23175-4-julien.grall@arm.com |
---|---|
State | Superseded |
Headers | show |
Series | xen/arm32: Branch predictor hardening (XSA-254 variant 2) | expand |
On Wed, 31 Jan 2018, Julien Grall wrote: > From: Julien Grall <julien.grall@linaro.org> > > At the moment, the reset vector is defined as .word 0 (e.g andeq r0, r0, > r0). > > This is rather unintuitive and will result to execute the trap > undefined. Instead introduce trap helpers for reset and will generate an > error message in the unlikely case that reset will be called. > > This is part of XSA-254. > > Signed-off-by: Julien Grall <julien.grall@linaro.org> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in v2: > - Replace .word 0 by trap_reset > --- > xen/arch/arm/arm32/entry.S | 3 ++- > xen/arch/arm/arm32/traps.c | 5 +++++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S > index c6490d2847..64876c1184 100644 > --- a/xen/arch/arm/arm32/entry.S > +++ b/xen/arch/arm/arm32/entry.S > @@ -137,7 +137,7 @@ trap_##trap: \ > > .align 5 > GLOBAL(hyp_traps_vector) > - .word 0 /* 0x00 - Reset */ > + b trap_reset /* 0x00 - Reset */ > b trap_undefined_instruction /* 0x04 - Undefined Instruction */ > b trap_hypervisor_call /* 0x08 - Hypervisor Call */ > b trap_prefetch_abort /* 0x0c - Prefetch Abort */ > @@ -146,6 +146,7 @@ GLOBAL(hyp_traps_vector) > b trap_irq /* 0x18 - IRQ */ > b trap_fiq /* 0x1c - FIQ */ > > +DEFINE_TRAP_ENTRY(reset) > DEFINE_TRAP_ENTRY(undefined_instruction) > DEFINE_TRAP_ENTRY(hypervisor_call) > DEFINE_TRAP_ENTRY(prefetch_abort) > diff --git a/xen/arch/arm/arm32/traps.c b/xen/arch/arm/arm32/traps.c > index 705255883e..4f27543dec 100644 > --- a/xen/arch/arm/arm32/traps.c > +++ b/xen/arch/arm/arm32/traps.c > @@ -23,6 +23,11 @@ > > #include <asm/processor.h> > > +void do_trap_reset(struct cpu_user_regs *regs) > +{ > + do_unexpected_trap("Reset", regs); > +} > + > void do_trap_undefined_instruction(struct cpu_user_regs *regs) > { > uint32_t pc = regs->pc; > -- > 2.11.0 >
diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index c6490d2847..64876c1184 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -137,7 +137,7 @@ trap_##trap: \ .align 5 GLOBAL(hyp_traps_vector) - .word 0 /* 0x00 - Reset */ + b trap_reset /* 0x00 - Reset */ b trap_undefined_instruction /* 0x04 - Undefined Instruction */ b trap_hypervisor_call /* 0x08 - Hypervisor Call */ b trap_prefetch_abort /* 0x0c - Prefetch Abort */ @@ -146,6 +146,7 @@ GLOBAL(hyp_traps_vector) b trap_irq /* 0x18 - IRQ */ b trap_fiq /* 0x1c - FIQ */ +DEFINE_TRAP_ENTRY(reset) DEFINE_TRAP_ENTRY(undefined_instruction) DEFINE_TRAP_ENTRY(hypervisor_call) DEFINE_TRAP_ENTRY(prefetch_abort) diff --git a/xen/arch/arm/arm32/traps.c b/xen/arch/arm/arm32/traps.c index 705255883e..4f27543dec 100644 --- a/xen/arch/arm/arm32/traps.c +++ b/xen/arch/arm/arm32/traps.c @@ -23,6 +23,11 @@ #include <asm/processor.h> +void do_trap_reset(struct cpu_user_regs *regs) +{ + do_unexpected_trap("Reset", regs); +} + void do_trap_undefined_instruction(struct cpu_user_regs *regs) { uint32_t pc = regs->pc;