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[192.237.175.120]) by mx.google.com with ESMTPS id n64si2079739ioe.147.2018.01.16.06.26.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jan 2018 06:26:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jj1/jeDq; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ebS9T-0002Ce-6S; Tue, 16 Jan 2018 14:23:47 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ebS9R-0002Ah-OJ for xen-devel@lists.xen.org; Tue, 16 Jan 2018 14:23:45 +0000 X-Inumbo-ID: a607d516-fac8-11e7-b4a6-bc764e045a96 Received: from mail-wm0-x241.google.com (unknown [2a00:1450:400c:c09::241]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id a607d516-fac8-11e7-b4a6-bc764e045a96; Tue, 16 Jan 2018 15:22:15 +0100 (CET) Received: by mail-wm0-x241.google.com with SMTP id b141so8807000wme.1 for ; Tue, 16 Jan 2018 06:23:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8wxFB9wGv1K4MQacAPmJ6ud6e+OKgjR/JREbUeMSJAA=; b=jj1/jeDqywapzlSOUFiM2E05dhkqDXZNoExbgtJ/u+M7RG9WaYBLwSmgsOwZwamtgl FnNht0BF/fLNNHaTwET60GRcd09CQIle4eI7ZcPWcKfrFon4nNqw+YjIphlqOTnL9EUG sAJYrJT/qPP66pNB1IvkZgtxEu1cZiRxHe1Z8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8wxFB9wGv1K4MQacAPmJ6ud6e+OKgjR/JREbUeMSJAA=; b=YsiJNcydFNxNiFCZua20e5z9FjQ4drTG6oRzBMqGaj4G/BGnvb3kudKSpE6QP+VtK3 ge+UGOuGVBamEHB6nZMMuhuEWj6FSmphVn3VwKsIYyAOvyzs6TCVfIdqQuOZNcW1jKxe r1br2OJloV8vWVPv+XMwbWBJDsWKXAsKiDNqG977NXG7OGeXeIq77fAFwMaQiclVasVj ympJTy7UUz6FtLhMrUvpiLpGLTNA81yWVZynNMplKz22AptTiQDxf6vu+zARgYJL/3Fk juakuXNVWvBmP+GlI6V6Rf7bgIohftph38js9GRatLppbQ5RFOsjVnEqderxXSTkNYFm +wYw== X-Gm-Message-State: AKwxytfWL/KMnR++2ld0HRLj4+g00I23gfw7WeM1z2B2l2nTwFKggiMb yH4/MMwKSPTaCmKI8nquqEZr5N0fY50= X-Received: by 10.28.237.20 with SMTP id l20mr12491731wmh.15.1516112623231; Tue, 16 Jan 2018 06:23:43 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id m201sm1686886wma.13.2018.01.16.06.23.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jan 2018 06:23:42 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 16 Jan 2018 14:23:34 +0000 Message-Id: <20180116142337.24942-3-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180116142337.24942-1-julien.grall@linaro.org> References: <20180116142337.24942-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, Julien Grall , andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 2/5] xen/arm64: Add missing MIDR values for Cortex-A72, A73 and A75 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Cortex-A72, A73 and A75 MIDR will be used to a follow-up for hardening the branch predictor. This is part of XSA-254. Signed-off-by: Julien Grall Acked-by: Stefano Stabellini --- xen/include/asm-arm/processor.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 65eb1071e1..3edab1b893 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -47,10 +47,16 @@ #define ARM_CPU_PART_CORTEX_A15 0xC0F #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 +#define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15) #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30)