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[192.237.175.120]) by mx.google.com with ESMTPS id m184si6251416ioa.80.2017.10.09.06.26.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Oct 2017 06:26:03 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e1Y2D-0007yH-44; Mon, 09 Oct 2017 13:23:53 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1e1Y2C-0007xj-40 for xen-devel@lists.xen.org; Mon, 09 Oct 2017 13:23:52 +0000 Received: from [85.158.139.211] by server-16.bemta-5.messagelabs.com id 36/91-01766-7687BD95; Mon, 09 Oct 2017 13:23:51 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTTet4na kwa9ec4slHxezODB6HN39mymAMYo1My8pvyKBNWPlxUmsBadFKtZfeczWwNgm0MXIxSEksJlR 4u3+LSwQzmlGiS+tk5i6GDk52AQ0Je58/gRmiwhIS1z7fJkRxGYWiJQ4/OEHO4gtLOAtMbP5E FicRUBV4tCbW2A2r4CFxKueZjYQW0JAXmJX20VWEJtTwFJi2ubpzCC2EFDN5Q87WCcwci9gZF jFqFGcWlSWWqRrZKmXVJSZnlGSm5iZo2toYKqXm1pcnJiempOYVKyXnJ+7iRHo4XoGBsYdjJe 3+B1ilORgUhLlnVJwO1KILyk/pTIjsTgjvqg0J7X4EKMMB4eSBK99OVBOsCg1PbUiLTMHGGow aQkOHiUR3lCQNG9xQWJucWY6ROoUoy5Hx827f5iEWPLy81KlxHmvlwEVCYAUZZTmwY2Ahf0lR lkpYV5GBgYGIZ6C1KLczBJU+VeM4hyMSsK8n0Cm8GTmlcBtegV0BBPQEYzFN0COKElESEk1MD LcfnKuXvSNcLHIslcq0oEvc/sFW1yrs+Xsz9/dl57Y7X9pRrxDRNFb9Ukn4l8f5np/rLx3NYe W6eIpVpsPy51dcjf7aIuX+9q+Qt6/L3JXOaxZ9mr2n4UTD3Q++ba+er3Obx7DB+dMHrKyau87 qq08I7t42Ux3TefjIqt3L54Y+3PL4cwuHiclluKMREMt5qLiRAA4i13zdgIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-15.tower-206.messagelabs.com!1507555430!92122566!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests=UPPERCASE_25_50 X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 65372 invoked from network); 9 Oct 2017 13:23:50 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-15.tower-206.messagelabs.com with SMTP; 9 Oct 2017 13:23:50 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 199491435; Mon, 9 Oct 2017 06:23:50 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2E03F3F578; Mon, 9 Oct 2017 06:23:49 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 9 Oct 2017 14:23:33 +0100 Message-Id: <20171009132341.1678-3-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171009132341.1678-1-julien.grall@arm.com> References: <20171009132341.1678-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v4 02/10] xen/arm: page: Clean-up the definition of MAIRVAL X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Currently MAIRVAL is defined in term of MAIR0VAL and MAIR1VAL which are both hardcoded value. This makes quite difficult to understand the value written in both registers. Rework the definition by using value of each attribute shifted by their associated index. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Changes in v3: - s/above/below/ in the comment - Add Stefano's reviewed-by Changes in v2: - Move this patch after "xen/arm: page: Use ARMv8 naming to improve readability" --- xen/include/asm-arm/page.h | 42 +++++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 3d0bc6db81..0ae1a2587b 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -22,6 +22,21 @@ #define LPAE_SH_INNER 0x3 /* + * Attribute Indexes. + * + * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page + * table entry. They are indexes into the bytes of the MAIR* + * registers, as defined below. + * + */ +#define MT_DEVICE_nGnRnE 0x0 +#define MT_NORMAL_NC 0x1 +#define MT_NORMAL_WT 0x2 +#define MT_NORMAL_WB 0x3 +#define MT_DEVICE_nGnRE 0x4 +#define MT_NORMAL 0x7 + +/* * LPAE Memory region attributes. Indexed by the AttrIndex bits of a * LPAE entry; the 8-bit fields are packed little-endian into MAIR0 and MAIR1. * @@ -38,24 +53,17 @@ * reserved 110 * MT_NORMAL 111 1111 1111 -- Write-back write-allocate */ -#define MAIR0VAL 0xeeaa4400 -#define MAIR1VAL 0xff000004 -#define MAIRVAL (MAIR0VAL|MAIR1VAL<<32) +#define MAIR(attr, mt) (_AC(attr, ULL) << ((mt) * 8)) -/* - * Attribute Indexes. - * - * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page - * table entry. They are indexes into the bytes of the MAIR* - * registers, as defined above. - * - */ -#define MT_DEVICE_nGnRnE 0x0 -#define MT_NORMAL_NC 0x1 -#define MT_NORMAL_WT 0x2 -#define MT_NORMAL_WB 0x3 -#define MT_DEVICE_nGnRE 0x4 -#define MT_NORMAL 0x7 +#define MAIRVAL (MAIR(0x00, MT_DEVICE_nGnRnE)| \ + MAIR(0x44, MT_NORMAL_NC) | \ + MAIR(0xaa, MT_NORMAL_WT) | \ + MAIR(0xee, MT_NORMAL_WB) | \ + MAIR(0x04, MT_DEVICE_nGnRE) | \ + MAIR(0xff, MT_NORMAL)) + +#define MAIR0VAL (MAIRVAL & 0xffffffff) +#define MAIR1VAL (MAIRVAL >> 32) #define PAGE_HYPERVISOR (MT_NORMAL) #define PAGE_HYPERVISOR_NOCACHE (MT_DEVICE_nGnRE)