From patchwork Thu Sep 14 17:08:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 112583 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp1002792qgf; Thu, 14 Sep 2017 10:11:20 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBtyGcAsiNkKntHpF2ISfTO/PJD5msVbfIMuih+cQN6cxQ6nOuR2XW3sgtLZBVjVJBMr1vQ X-Received: by 10.36.201.196 with SMTP id h187mr1078944itg.42.1505409080145; Thu, 14 Sep 2017 10:11:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505409080; cv=none; d=google.com; s=arc-20160816; b=ukLRaVO+8PlkowLIDxW7EAhvb6dbxOAxYwoYE6EI27ppX65pc1v2VFv3DCf+OrQMHL JlhKJ5MpN6cZb+Y30PHeVLnWLAWIeu84eVUtvbCq4U8ZVQVd7cTyB9FFH/Zg/nzpGjiS Fi/AE5tX3nLBgx8/g49HeUquElTqF0+L5QVuaapuB+SL026Ejz14QZa8VTWw8MwOty5Q qKoIvJA18DvVvOK/bJsDdIPUhfewXIqUNzFNzmvw2Cj6BtqQa4gwphuA2mTZqSM80DoC dyUO0cFtqjBax+9S6KSBv4x4K/PNUw1URGItIUs+W4BFR3Noz3o9VnsQ1jkxT+tNlDLJ buWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=ce+lvpHHNU9A+uetqB2GLz3wEVC6NCeBS/kzAlY6YKo=; b=k3oLKNJrcbAInPRk0kov4/FA1ioUvf6BkKaj08I8iG4G41jrUw2MtxPOj9lliWmeRz i0rTMoS/qwA/x0RdQU8b9a3rcGhDRttLa0rne5zA4PTnaO6CBptdtmhsMBNJvD4vvW+R HAT8Kz+6x31FaJ7wPiVUmdwTLJoKQxTj1miN1Ro8PkiJUtGswoqQacVW/lBe4J8KTP8R tnGMJvtbtZYgyxcYkA89Zd5titafIe7EN33ea0E7ejQA6rWyAQt8i+r0KnL5bYAJ/jDw xrd8aOcHJt35lZR/LiA9meXz7VOzG5+tWgCNRBh0lRkSK1XsVAHZW++j00YF7roGT1n/ m38Q== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g21si486575itg.121.2017.09.14.10.11.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Sep 2017 10:11:20 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdZ-0008DG-1F; Thu, 14 Sep 2017 17:09:13 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dsXdX-0008Bi-GU for xen-devel@lists.xen.org; Thu, 14 Sep 2017 17:09:11 +0000 Received: from [85.158.137.68] by server-14.bemta-3.messagelabs.com id FA/0B-01910-6B7BAB95; Thu, 14 Sep 2017 17:09:10 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRWlGSWpSXmKPExsVysyfVTXfL9l2 RBiffMlss+biYxYHR4+ju30wBjFGsmXlJ+RUJrBnTr8xhLfhrWrF42TfmBsanGl2MXBxCApsZ JfYeW8kC4ZxmlFh26TRrFyMnB5uApsSdz5+YQGwRAWmJa58vM4LYzALVEv8XnmQDsYUFQiXeP NnBDGKzCKhK7JlyAqyeV8BSYtK6nSwgtoSAvMSutotgMzkFrCR2/74CVi8EVLPrzlf2CYzcCx gZVjFqFKcWlaUW6RqZ6SUVZaZnlOQmZuboGhoY6+WmFhcnpqfmJCYV6yXn525iBHq4noGBcQd jw16/Q4ySHExKorx7dXdGCvEl5adUZiQWZ8QXleakFh9ilOHgUJLgnb5tV6SQYFFqempFWmYO MNRg0hIcPEoivHkgad7igsTc4sx0iNQpRl2Ojpt3/zAJseTl56VKifPWgRQJgBRllObBjYCF/ SVGWSlhXkYGBgYhnoLUotzMElT5V4ziHIxKwrxVIFN4MvNK4Da9AjqCCeiIM6d3gBxRkoiQkm pgrOrzFo+x22NbvkliF5PA9aAms713A1b9eP14vhFfnrXVx7VzQ7TnbJjf+V7+qoeM2scZSYs uPpGuuXw/yynxa/LVsCdxnnM0wkzi71VfaePdfEQ5+PXWer1go0lX+ljmKn35vJll/nMVBeE7 3z/fkDDjzBX9/O3j/ulNsqzvbSri7dU9e6v+K7EUZyQaajEXFScCAGusfOx2AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-16.tower-31.messagelabs.com!1505408947!107232161!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48579 invoked from network); 14 Sep 2017 17:09:07 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-16.tower-31.messagelabs.com with SMTP; 14 Sep 2017 17:09:07 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 239BC1435; Thu, 14 Sep 2017 10:09:07 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 11B323F483; Thu, 14 Sep 2017 10:09:05 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 14 Sep 2017 18:08:55 +0100 Message-Id: <20170914170859.30553-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170914170859.30553-1-julien.grall@arm.com> References: <20170914170859.30553-1-julien.grall@arm.com> Cc: bhupinder.thakur@linaro.org, Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH v3 1/5] xen/arm: traps: Export a bunch of helpers to handle emulation X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" A follow-up patch will move some parts of traps.c in separate files. The will require to use helpers that are currently statically defined. Export the following helpers: - inject_undef64_exception - inject_undef_exception - check_conditional_instr - advance_pc - handle_raz_wi - handle_wo_wi - handle_ro_raz Note that asm-arm/arm32/traps.h is empty but it is to keep parity with the arm64 counterpart. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- Cc: volodymyr_babchuk@epam.com Changes in v3: - Replicate comment on top of each prototypes when useful Changes in v2: - Fixup guards - Add newline for clarity --- xen/arch/arm/traps.c | 43 +++++++++++++++++++-------------------- xen/include/asm-arm/arm32/traps.h | 13 ++++++++++++ xen/include/asm-arm/arm64/traps.h | 15 ++++++++++++++ xen/include/asm-arm/traps.h | 39 +++++++++++++++++++++++++++++++++++ 4 files changed, 88 insertions(+), 22 deletions(-) create mode 100644 xen/include/asm-arm/arm32/traps.h create mode 100644 xen/include/asm-arm/arm64/traps.h create mode 100644 xen/include/asm-arm/traps.h diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 6f32f700e5..1c334a7b99 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -547,7 +548,7 @@ static vaddr_t exception_handler64(struct cpu_user_regs *regs, vaddr_t offset) } /* Inject an undefined exception into a 64 bit guest */ -static void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) +void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len) { vaddr_t handler; const union hsr esr = { @@ -620,8 +621,7 @@ static void inject_iabt64_exception(struct cpu_user_regs *regs, #endif -static void inject_undef_exception(struct cpu_user_regs *regs, - const union hsr hsr) +void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr) { if ( is_32bit_domain(current->domain) ) inject_undef32_exception(regs); @@ -1714,8 +1714,7 @@ static const unsigned short cc_map[16] = { 0 /* NV */ }; -static int check_conditional_instr(struct cpu_user_regs *regs, - const union hsr hsr) +int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long cpsr, cpsr_cond; int cond; @@ -1777,7 +1776,7 @@ static int check_conditional_instr(struct cpu_user_regs *regs, return 1; } -static void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) +void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) { unsigned long itbits, cond, cpsr = regs->cpsr; @@ -1818,11 +1817,11 @@ static void advance_pc(struct cpu_user_regs *regs, const union hsr hsr) } /* Read as zero and write ignore */ -static void handle_raz_wi(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +void handle_raz_wi(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); @@ -1836,12 +1835,12 @@ static void handle_raz_wi(struct cpu_user_regs *regs, advance_pc(regs, hsr); } -/* Write only as write ignore */ -static void handle_wo_wi(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +/* write only as write ignore */ +void handle_wo_wi(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); @@ -1856,11 +1855,11 @@ static void handle_wo_wi(struct cpu_user_regs *regs, } /* Read only as read as zero */ -static void handle_ro_raz(struct cpu_user_regs *regs, - int regidx, - bool read, - const union hsr hsr, - int min_el) +void handle_ro_raz(struct cpu_user_regs *regs, + int regidx, + bool read, + const union hsr hsr, + int min_el) { ASSERT((min_el == 0) || (min_el == 1)); diff --git a/xen/include/asm-arm/arm32/traps.h b/xen/include/asm-arm/arm32/traps.h new file mode 100644 index 0000000000..e3c4a8b473 --- /dev/null +++ b/xen/include/asm-arm/arm32/traps.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ARM32_TRAPS__ +#define __ASM_ARM32_TRAPS__ + +#endif /* __ASM_ARM32_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/asm-arm/arm64/traps.h b/xen/include/asm-arm/arm64/traps.h new file mode 100644 index 0000000000..e5e5a4a036 --- /dev/null +++ b/xen/include/asm-arm/arm64/traps.h @@ -0,0 +1,15 @@ +#ifndef __ASM_ARM64_TRAPS__ +#define __ASM_ARM64_TRAPS__ + +void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len); + +#endif /* __ASM_ARM64_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h new file mode 100644 index 0000000000..22ad070679 --- /dev/null +++ b/xen/include/asm-arm/traps.h @@ -0,0 +1,39 @@ +#ifndef __ASM_ARM_TRAPS__ +#define __ASM_ARM_TRAPS__ + +#include + +#if defined(CONFIG_ARM_32) +# include +#elif defined(CONFIG_ARM_64) +# include +#endif + +int check_conditional_instr(struct cpu_user_regs *regs, const union hsr hsr); + +void advance_pc(struct cpu_user_regs *regs, const union hsr hsr); + +void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr); + +/* read as zero and write ignore */ +void handle_raz_wi(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +/* write only as write ignore */ +void handle_wo_wi(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +/* read only as read as zero */ +void handle_ro_raz(struct cpu_user_regs *regs, int regidx, bool read, + const union hsr hsr, int min_el); + +#endif /* __ASM_ARM_TRAPS__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ +