From patchwork Mon Aug 14 14:24:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 110012 Delivered-To: patch@linaro.org Received: by 10.182.109.195 with SMTP id hu3csp4281678obb; Mon, 14 Aug 2017 07:26:23 -0700 (PDT) X-Received: by 10.107.166.203 with SMTP id p194mr19624953ioe.48.1502720783242; Mon, 14 Aug 2017 07:26:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502720783; cv=none; d=google.com; s=arc-20160816; b=kxCBUG4JHbDLYhcFRXDMIISKDcrVc137Tp3BKvXZfalLuQ3ZlvEV+C2xB8yxqwB7kg ggnXy0aHaPLQkrLVBdYT5Zla3Fje78lAi+VTyje0MNK/p1dKFKiSKeGloRJXAnPZSUSJ WgiTsKAB2bqhF7kyw/k2EqzwMhQeusqXzKcSiQZGVA5TZFhxrB38YKzlPm2rmqq/U8tm 7zPZtp79KlZKV6RZ4m4/ZX7hmnjjniFRXNmFd7NDHQZHsctmH9/E1CV8MWumNtPwY0Ns kn7xtv/blAZ3ISwtsGyklN/al7jejpZlr7C2Lrwa+emqZTTs6vA2CvrdLwqx/3IhmLT1 G1mA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=KbHu5TQmDA8amR44wJ8illWwPhasNe9UxUwLFdjB3cI=; b=e2/yD09HJ/oHbTV9gyGp4iJztXdkV97v5qYvycIWhfXo2niF99Ic+h5i0kJu0FS5p2 XGSvoUeGS0kkbZHXGFnkeup/0lP5eXxBh6RAuwEfHkj2k6kYXAaf+dpR6Ly5MnsaPjHT SZUlEdzpnuDQ0sCbFo/h0Bl37y+9FlWCw4t1uCXtORrZ6Vrfjow6yZlztGPP58A/1lAB IY+HNSa2dQ2w3V4VTiJYLGHEaz4ci2hgVPnt4JWp6C1t0bVkEwoz07RUPD+PWZuAbNdz wJi8Tu2eh8vyCaUoYJX2wImYtWIAd8UlLVtTrQ7qHU7puyOce30+w9h4iWyjh15mFp96 sBxg== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g63si5489807ita.145.2017.08.14.07.26.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Aug 2017 07:26:23 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dhGId-0000nl-PW; Mon, 14 Aug 2017 14:24:59 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dhGIc-0000iU-Gm for xen-devel@lists.xen.org; Mon, 14 Aug 2017 14:24:58 +0000 Received: from [193.109.254.147] by server-4.bemta-6.messagelabs.com id AC/7B-02962-8B2B1995; Mon, 14 Aug 2017 14:24:56 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJLMWRWlGSWpSXmKPExsVysyfVTXfHpom RBjv+cVss+biYxYHR4+ju30wBjFGsmXlJ+RUJrBkbJ55lLLjmUfFyZQ9zA+Nl8y5GLg4hgc2M EptnfmGFcE4zSsz89J6li5GTg01AU+LO509MILaIgLTEtc+XGUFsZoFIicMffrCD2MICThLXm g+D1bMIqErsadgHVs8rYCUxYe8NNhBbQkBeYlfbRVYQmxMo3nl3J1i9kIClxInVs9kmMHIvYG RYxahRnFpUllqka2iil1SUmZ5RkpuYmaNraGCml5taXJyYnpqTmFSsl5yfu4kR6GEGINjBeH1 jwCFGSQ4mJVHeBJ/eSCG+pPyUyozE4oz4otKc1OJDjDIcHEoSvKkbJ0YKCRalpqdWpGXmAEMN Ji3BwaMkwnsDJM1bXJCYW5yZDpE6xWjM0THj5zcmjlcT/n9jEmLJy89LlRLnLQcpFQApzSjNg xsEi4FLjLJSwryMQKcJ8RSkFuVmlqDKv2IU52BUEubdDDKFJzOvBG7fK6BTmIBO6QP5gre4JB EhJdXAuN7jahHn2sMXTxqGyaz6YvrWnf/n28LynYvtS/m3zskoL+kW/LC3fatu5EvJBpVX+cs Xe+s6RAY9OXH/6leniNvuvBYKGUJHSpb/+mm76NSy4GDmsI0te6TVbEJ+cOxe+UGXOehx/abu BQazVY0WbxRLeKmgwrh5rmShk5ncQ1PZhw97XnyaqcRSnJFoqMVcVJwIAAps8fV8AgAA X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-13.tower-27.messagelabs.com!1502720695!102211476!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3735 invoked from network); 14 Aug 2017 14:24:55 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-13.tower-27.messagelabs.com with SMTP; 14 Aug 2017 14:24:55 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 42AE81713; Mon, 14 Aug 2017 07:24:55 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 33A6C3F483; Mon, 14 Aug 2017 07:24:54 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 14 Aug 2017 15:24:09 +0100 Message-Id: <20170814142418.13267-19-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170814142418.13267-1-julien.grall@arm.com> References: <20170814142418.13267-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 18/27] xen/arm: page: Prefix memory types with MT_ X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" This will avoid confusion in the code when using them. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/arch/arm/kernel.c | 2 +- xen/arch/arm/mm.c | 28 +++++++++++++-------------- xen/arch/arm/platforms/vexpress.c | 2 +- xen/drivers/video/arm_hdlcd.c | 2 +- xen/include/asm-arm/page.h | 40 +++++++++++++++++++-------------------- 5 files changed, 37 insertions(+), 37 deletions(-) diff --git a/xen/arch/arm/kernel.c b/xen/arch/arm/kernel.c index 7403ec0c0e..9c183f96da 100644 --- a/xen/arch/arm/kernel.c +++ b/xen/arch/arm/kernel.c @@ -54,7 +54,7 @@ void copy_from_paddr(void *dst, paddr_t paddr, unsigned long len) s = paddr & (PAGE_SIZE-1); l = min(PAGE_SIZE - s, len); - set_fixmap(FIXMAP_MISC, maddr_to_mfn(paddr), BUFFERABLE); + set_fixmap(FIXMAP_MISC, maddr_to_mfn(paddr), MT_BUFFERABLE); memcpy(dst, src + s, l); clean_dcache_va_range(dst, l); diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 349ac58ffe..45974846a9 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -290,7 +290,7 @@ static inline lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned attr) switch ( attr ) { - case BUFFERABLE: + case MT_BUFFERABLE: /* * ARM ARM: Overlaying the shareability attribute (DDI * 0406C.b B3-1376 to 1377) @@ -305,8 +305,8 @@ static inline lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned attr) */ e.pt.sh = LPAE_SH_OUTER; break; - case UNCACHED: - case DEV_SHARED: + case MT_UNCACHED: + case MT_DEV_SHARED: /* * Shareability is ignored for non-Normal memory, Outer is as * good as anything. @@ -369,7 +369,7 @@ static void __init create_mappings(lpae_t *second, count = nr_mfns / LPAE_ENTRIES; p = second + second_linear_offset(virt_offset); - pte = mfn_to_xen_entry(_mfn(base_mfn), WRITEALLOC); + pte = mfn_to_xen_entry(_mfn(base_mfn), MT_WRITEALLOC); if ( granularity == 16 * LPAE_ENTRIES ) pte.pt.contig = 1; /* These maps are in 16-entry contiguous chunks. */ for ( i = 0; i < count; i++ ) @@ -422,7 +422,7 @@ void *map_domain_page(mfn_t mfn) else if ( map[slot].pt.avail == 0 ) { /* Commandeer this 2MB slot */ - pte = mfn_to_xen_entry(_mfn(slot_mfn), WRITEALLOC); + pte = mfn_to_xen_entry(_mfn(slot_mfn), MT_WRITEALLOC); pte.pt.avail = 1; write_pte(map + slot, pte); break; @@ -543,7 +543,7 @@ static inline lpae_t pte_of_xenaddr(vaddr_t va) { paddr_t ma = va + phys_offset; - return mfn_to_xen_entry(maddr_to_mfn(ma), WRITEALLOC); + return mfn_to_xen_entry(maddr_to_mfn(ma), MT_WRITEALLOC); } /* Map the FDT in the early boot page table */ @@ -652,7 +652,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr) /* Initialise xen second level entries ... */ /* ... Xen's text etc */ - pte = mfn_to_xen_entry(maddr_to_mfn(xen_paddr), WRITEALLOC); + pte = mfn_to_xen_entry(maddr_to_mfn(xen_paddr), MT_WRITEALLOC); pte.pt.xn = 0;/* Contains our text mapping! */ xen_second[second_table_offset(XEN_VIRT_START)] = pte; @@ -669,7 +669,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr) /* ... Boot Misc area for xen relocation */ dest_va = BOOT_RELOC_VIRT_START; - pte = mfn_to_xen_entry(maddr_to_mfn(xen_paddr), WRITEALLOC); + pte = mfn_to_xen_entry(maddr_to_mfn(xen_paddr), MT_WRITEALLOC); /* Map the destination in xen_second. */ xen_second[second_table_offset(dest_va)] = pte; /* Map the destination in boot_second. */ @@ -700,7 +700,7 @@ void __init setup_pagetables(unsigned long boot_phys_offset, paddr_t xen_paddr) unsigned long va = XEN_VIRT_START + (i << PAGE_SHIFT); if ( !is_kernel(va) ) break; - pte = mfn_to_xen_entry(mfn, WRITEALLOC); + pte = mfn_to_xen_entry(mfn, MT_WRITEALLOC); pte.pt.table = 1; /* 4k mappings always have this bit set */ if ( is_kernel_text(va) || is_kernel_inittext(va) ) { @@ -771,7 +771,7 @@ int init_secondary_pagetables(int cpu) for ( i = 0; i < DOMHEAP_SECOND_PAGES; i++ ) { pte = mfn_to_xen_entry(virt_to_mfn(domheap+i*LPAE_ENTRIES), - WRITEALLOC); + MT_WRITEALLOC); pte.pt.table = 1; write_pte(&first[first_table_offset(DOMHEAP_VIRT_START+i*FIRST_SIZE)], pte); } @@ -869,13 +869,13 @@ void __init setup_xenheap_mappings(unsigned long base_mfn, mfn_t first_mfn = alloc_boot_pages(1, 1); clear_page(mfn_to_virt(first_mfn)); - pte = mfn_to_xen_entry(first_mfn, WRITEALLOC); + pte = mfn_to_xen_entry(first_mfn, MT_WRITEALLOC); pte.pt.table = 1; write_pte(p, pte); first = mfn_to_virt(first_mfn); } - pte = mfn_to_xen_entry(_mfn(mfn), WRITEALLOC); + pte = mfn_to_xen_entry(_mfn(mfn), MT_WRITEALLOC); /* TODO: Set pte.pt.contig when appropriate. */ write_pte(&first[first_table_offset(vaddr)], pte); @@ -915,7 +915,7 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) for ( i = 0; i < nr_second; i++ ) { clear_page(mfn_to_virt(mfn_add(second_base, i))); - pte = mfn_to_xen_entry(mfn_add(second_base, i), WRITEALLOC); + pte = mfn_to_xen_entry(mfn_add(second_base, i), MT_WRITEALLOC); pte.pt.table = 1; write_pte(&xen_first[first_table_offset(FRAMETABLE_VIRT_START)+i], pte); } @@ -969,7 +969,7 @@ static int create_xen_table(lpae_t *entry) if ( p == NULL ) return -ENOMEM; clear_page(p); - pte = mfn_to_xen_entry(virt_to_mfn(p), WRITEALLOC); + pte = mfn_to_xen_entry(virt_to_mfn(p), MT_WRITEALLOC); pte.pt.table = 1; write_pte(entry, pte); return 0; diff --git a/xen/arch/arm/platforms/vexpress.c b/xen/arch/arm/platforms/vexpress.c index a26ac324ba..9badbc079d 100644 --- a/xen/arch/arm/platforms/vexpress.c +++ b/xen/arch/arm/platforms/vexpress.c @@ -65,7 +65,7 @@ int vexpress_syscfg(int write, int function, int device, uint32_t *data) uint32_t *syscfg = (uint32_t *) FIXMAP_ADDR(FIXMAP_MISC); int ret = -1; - set_fixmap(FIXMAP_MISC, maddr_to_mfn(V2M_SYS_MMIO_BASE), DEV_SHARED); + set_fixmap(FIXMAP_MISC, maddr_to_mfn(V2M_SYS_MMIO_BASE), MT_DEV_SHARED); if ( syscfg[V2M_SYS_CFGCTRL/4] & V2M_SYS_CFG_START ) goto out; diff --git a/xen/drivers/video/arm_hdlcd.c b/xen/drivers/video/arm_hdlcd.c index 3915f731f5..5fa7f518b1 100644 --- a/xen/drivers/video/arm_hdlcd.c +++ b/xen/drivers/video/arm_hdlcd.c @@ -227,7 +227,7 @@ void __init video_init(void) /* uses FIXMAP_MISC */ set_pixclock(videomode->pixclock); - set_fixmap(FIXMAP_MISC, maddr_to_mfn(hdlcd_start), DEV_SHARED); + set_fixmap(FIXMAP_MISC, maddr_to_mfn(hdlcd_start), MT_DEV_SHARED); HDLCD[HDLCD_COMMAND] = 0; HDLCD[HDLCD_LINELENGTH] = videomode->xres * bytes_per_pixel; diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 660e1779c5..d7a048b64d 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -25,17 +25,17 @@ * LPAE Memory region attributes. Indexed by the AttrIndex bits of a * LPAE entry; the 8-bit fields are packed little-endian into MAIR0 and MAIR1. * - * ai encoding - * UNCACHED 000 0000 0000 -- Strongly Ordered - * BUFFERABLE 001 0100 0100 -- Non-Cacheable - * WRITETHROUGH 010 1010 1010 -- Write-through - * WRITEBACK 011 1110 1110 -- Write-back - * DEV_SHARED 100 0000 0100 -- Device - * ?? 101 - * reserved 110 - * WRITEALLOC 111 1111 1111 -- Write-back write-allocate + * ai encoding + * MT_UNCACHED 000 0000 0000 -- Strongly Ordered + * MT_BUFFERABLE 001 0100 0100 -- Non-Cacheable + * MT_WRITETHROUGH 010 1010 1010 -- Write-through + * MT_WRITEBACK 011 1110 1110 -- Write-back + * MT_DEV_SHARED 100 0000 0100 -- Device + * ?? 101 + * reserved 110 + * MT_WRITEALLOC 111 1111 1111 -- Write-back write-allocate * - * DEV_WC 001 (== BUFFERABLE) + * MT_DEV_WC 001 (== BUFFERABLE) */ #define MAIR0VAL 0xeeaa4400 #define MAIR1VAL 0xff000004 @@ -49,16 +49,16 @@ * registers, as defined above. * */ -#define UNCACHED 0x0 -#define BUFFERABLE 0x1 -#define WRITETHROUGH 0x2 -#define WRITEBACK 0x3 -#define DEV_SHARED 0x4 -#define WRITEALLOC 0x7 - -#define PAGE_HYPERVISOR (WRITEALLOC) -#define PAGE_HYPERVISOR_NOCACHE (DEV_SHARED) -#define PAGE_HYPERVISOR_WC (BUFFERABLE) +#define MT_UNCACHED 0x0 +#define MT_BUFFERABLE 0x1 +#define MT_WRITETHROUGH 0x2 +#define MT_WRITEBACK 0x3 +#define MT_DEV_SHARED 0x4 +#define MT_WRITEALLOC 0x7 + +#define PAGE_HYPERVISOR (MT_WRITEALLOC) +#define PAGE_HYPERVISOR_NOCACHE (MT_DEV_SHARED) +#define PAGE_HYPERVISOR_WC (MT_BUFFERABLE) /* * Defines for changing the hypervisor PTE .ro and .nx bits. This is only to be