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[192.237.175.120]) by mx.google.com with ESMTPS id 191si7815345iof.51.2017.06.30.08.57.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Jun 2017 08:57:13 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dQyFu-0000XV-3X; Fri, 30 Jun 2017 15:54:50 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dQyFs-0000Ut-BL for xen-devel@lists.xen.org; Fri, 30 Jun 2017 15:54:48 +0000 Received: from [193.109.254.147] by server-2.bemta-6.messagelabs.com id DF/53-03032-74476595; Fri, 30 Jun 2017 15:54:47 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPLMWRWlGSWpSXmKPExsVysyfVTdetJCz SYF+DucWSj4tZHBg9ju7+zRTAGMWamZeUX5HAmrFvxVv2gkuqFUueCDcwdst0MXJxCAlsYpR4 /HMfC4RzmlHi08TjbF2MnBxsApoSdz5/YgKxRQSkJa59vszYxcjBwSwQJfF/GieIKSzgJPF8r xRIBYuAqsTG71uZQWxeASuJ/8dnsYLYEgLyErvaLoLZnEDx4/8egE0UErCUeD3rKssERu4FjA yrGNWLU4vKUot0zfSSijLTM0pyEzNzdA0NzPRyU4uLE9NTcxKTivWS83M3MQI9ywAEOxjnnfA /xCjJwaQkyrvyWmikEF9SfkplRmJxRnxRaU5q8SFGGQ4OJQlexeKwSCHBotT01Iq0zBxgiMGk JTh4lER4ZYOA0rzFBYm5xZnpEKlTjLocryb8/8YkxJKXn5cqJc77qgioSACkKKM0D24ELNwvM cpKCfMyAh0lxFOQWpSbWYIq/4pRnINRSZj3JMgUnsy8ErhNr4COYAI6QnhGCMgRJYkIKakGxv 5Hm79vjf4w6aizx/nJbZ+Me1oW7zc4rphp8Lz2a1bv9n17z2wrXLFEan3eefGf2/+UVF7XybX /sSc7yUWr81OGZvG1dINtwrM6Z56517bWf2/yl2uGa+/+126f4/jn73p3lqm3/Of1b96+SbSq +Izw2v5TxuFlVb17J0apbRXZyumx89i9mJ1KLMUZiYZazEXFiQAl3k4fcgIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1498838086!92584177!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.25; banners=-,-,- X-VirusChecked: Checked Received: (qmail 8614 invoked from network); 30 Jun 2017 15:54:46 -0000 Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-14.tower-27.messagelabs.com with SMTP; 30 Jun 2017 15:54:46 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1195980D; Fri, 30 Jun 2017 08:54:46 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 50FB43F41F; Fri, 30 Jun 2017 08:54:45 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 30 Jun 2017 16:54:25 +0100 Message-Id: <20170630155431.23824-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170630155431.23824-1-julien.grall@arm.com> References: <20170630155431.23824-1-julien.grall@arm.com> Cc: proskurin@sec.in.tum.de, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH v3 10/16] xen/arm: lpae: Fix comments coding style X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" Also adding one missing full stop + fix description Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini Reviewed-by: Sergej Proskurin --- Cc: proskurin@sec.in.tum.de I haven't retained Stefano's reviewed-by because of the description update. Changes in v2: - Fix description regarding x86 page-table Changes in v3: - Add Stefano's reviewed-by --- xen/include/asm-arm/lpae.h | 49 ++++++++++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/xen/include/asm-arm/lpae.h b/xen/include/asm-arm/lpae.h index ad8c571ea5..aa85cb8112 100644 --- a/xen/include/asm-arm/lpae.h +++ b/xen/include/asm-arm/lpae.h @@ -3,10 +3,12 @@ #ifndef __ASSEMBLY__ -/* WARNING! Unlike the Intel pagetable code, where l1 is the lowest - * level and l4 is the root of the trie, the ARM pagetables follow ARM's - * documentation: the levels are called first, second &c in the order - * that the MMU walks them (i.e. "first" is the root of the trie). */ +/* + * WARNING! Unlike the x86 pagetable code, where l1 is the lowest level and + * l4 is the root of the trie, the ARM pagetables follow ARM's documentation: + * the levels are called first, second &c in the order that the MMU walks them + * (i.e. "first" is the root of the trie). + */ /****************************************************************************** * ARMv7-A LPAE pagetables: 3-level trie, mapping 40-bit input to @@ -17,15 +19,18 @@ * different place from those in leaf nodes seems to be to allow linear * pagetable tricks. If we're not doing that then the set of permission * bits that's not in use in a given node type can be used as - * extra software-defined bits. */ + * extra software-defined bits. + */ typedef struct __packed { /* These are used in all kinds of entry. */ unsigned long valid:1; /* Valid mapping */ unsigned long table:1; /* == 1 in 4k map entries too */ - /* These ten bits are only used in Block entries and are ignored - * in Table entries. */ + /* + * These ten bits are only used in Block entries and are ignored + * in Table entries. + */ unsigned long ai:3; /* Attribute Index */ unsigned long ns:1; /* Not-Secure */ unsigned long user:1; /* User-visible */ @@ -38,30 +43,38 @@ typedef struct __packed { unsigned long long base:36; /* Base address of block or next table */ unsigned long sbz:4; /* Must be zero */ - /* These seven bits are only used in Block entries and are ignored - * in Table entries. */ + /* + * These seven bits are only used in Block entries and are ignored + * in Table entries. + */ unsigned long contig:1; /* In a block of 16 contiguous entries */ unsigned long pxn:1; /* Privileged-XN */ unsigned long xn:1; /* eXecute-Never */ unsigned long avail:4; /* Ignored by hardware */ - /* These 5 bits are only used in Table entries and are ignored in - * Block entries */ + /* + * These 5 bits are only used in Table entries and are ignored in + * Block entries. + */ unsigned long pxnt:1; /* Privileged-XN */ unsigned long xnt:1; /* eXecute-Never */ unsigned long apt:2; /* Access Permissions */ unsigned long nst:1; /* Not-Secure */ } lpae_pt_t; -/* The p2m tables have almost the same layout, but some of the permission - * and cache-control bits are laid out differently (or missing) */ +/* + * The p2m tables have almost the same layout, but some of the permission + * and cache-control bits are laid out differently (or missing). + */ typedef struct __packed { /* These are used in all kinds of entry. */ unsigned long valid:1; /* Valid mapping */ unsigned long table:1; /* == 1 in 4k map entries too */ - /* These ten bits are only used in Block entries and are ignored - * in Table entries. */ + /* + * These ten bits are only used in Block entries and are ignored + * in Table entries. + */ unsigned long mattr:4; /* Memory Attributes */ unsigned long read:1; /* Read access */ unsigned long write:1; /* Write access */ @@ -73,8 +86,10 @@ typedef struct __packed { unsigned long long base:36; /* Base address of block or next table */ unsigned long sbz3:4; - /* These seven bits are only used in Block entries and are ignored - * in Table entries. */ + /* + * These seven bits are only used in Block entries and are ignored + * in Table entries. + */ unsigned long contig:1; /* In a block of 16 contiguous entries */ unsigned long sbz2:1; unsigned long xn:1; /* eXecute-Never */