From patchwork Thu Jun 15 20:30:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 105690 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp982679qgd; Thu, 15 Jun 2017 13:33:17 -0700 (PDT) X-Received: by 10.36.51.82 with SMTP id k79mr7456426itk.32.1497558797528; Thu, 15 Jun 2017 13:33:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497558797; cv=none; d=google.com; s=arc-20160816; b=1JU8eDT3Hv2lIIxsS81h3WXyFc56CMweMkAK0p6530zlkuSeTYCgVe2vLUV8eXP0w0 YMo6SEuk+sP2SYC6EdRiYxqi0VO52UPs9yVsMR76R7irkM4I7LoQHk9SUz/LCYYIN2Ww DzIQV6yJJvgIrLdfTGrj9c20WMup3wnqkLD6K5fMSduDTxixfQ1UFGQUX5kAztG0uSEp KFjZVrvMeej+9r3YkIt2ULJ1JBGp4CzF+2QvHV43GuLJjmPpFlFIlJQsWecBBrlC0FVB igB32crTMYY/eCDs3VFtMy/6zJETxufpbT2vKVgQxC3GgkXvTwLiAT6tJeqtWa52s2Jr 85vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=mXTE2CjugzatPyABMwDDbI6hdCUgDALrH5HNQq+wk7k=; b=FpM4TI8VSSbDtg7MeWbk8Hrk2Re6CVDTihvaytKuvp9oz+22Iv9udoDgBHIzHgFns9 DctMNXF+IhTBBRV6HePRCjFaZCu7vWaoiymzVhSp08/cieZLvCwrgG7KFZj0O0/uvU9r /hxLs+R2/8BNYM6HsCviVWfl5GFZctMZCIQVvBQREM0OK7b5djl6rQkKqpeTEQdZFYxj W3s70afx8sNTev7gE3WNZDAOyol0YOWB9W+k9Q0Ovtaed7fGDipzXyk6SNclWGaS8Gkt Jo9YR46zvrmHkTq0raMmMjLVJv5jV9qYub1/N5M3X51bUGNw/sA1EVY7YP9fWcJJC3UZ FHBA== ARC-Authentication-Results: i=1; mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id g33si248468iod.163.2017.06.15.13.33.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Jun 2017 13:33:17 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dLbQ8-0001WF-Mv; Thu, 15 Jun 2017 20:31:12 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dLbQ6-0001Vs-TU for xen-devel@lists.xen.org; Thu, 15 Jun 2017 20:31:11 +0000 Received: from [85.158.137.68] by server-16.bemta-3.messagelabs.com id C8/46-29088-E8EE2495; Thu, 15 Jun 2017 20:31:10 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRWlGSWpSXmKPExsVysyfVTbf3nVO kwecJghZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bJyU/YC9YVVtx/2cnewLgwsouRk0NIYDOj xK0tOl2MXED2aUaJZweXsIMk2AQ0Je58/sQEYosISEtc+3yZEcRmFoiSaL69FKxGWMBd4uL0r awgNouAqsTxzg6wOK+AuUTjir9gvRIC8hK72i6C1XAKWEhsftXMBLHYXOLFg072CYzcCxgZVj FqFKcWlaUW6RoZ6yUVZaZnlOQmZuboGhoY6+WmFhcnpqfmJCYV6yXn525iBPq3noGBcQdj316 /Q4ySHExKorz8ck6RQnxJ+SmVGYnFGfFFpTmpxYcYZTg4lCR4u94C5QSLUtNTK9Iyc4CBBpOW 4OBREuFlfwyU5i0uSMwtzkyHSJ1iVJQS51UB6RMASWSU5sG1wYL7EqOslDAvIwMDgxBPQWpRb mYJqvwrRnEORiVhXn6QKTyZeSVw018BLWYCWhx0wQFkcUkiQkqqgXFz24rjEdtmf1LYfiHpxs pvhRWbw/quGvW0O0yKeHVTPHT5ltU7bZV4X3BbsDbrX+xdYL/Xe/0Ta9Zdky9v8S6cWJlqzXF +dqFkouP1qJXPz+offSnHEv5mXuTdjzu5a0S+PeAxfVt4Na/hw6u5856eXh9WHGVd43drId9s LpF9UmuX1ejpnWdTYinOSDTUYi4qTgQAYl6JYWkCAAA= X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1497558668!101017764!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.19; banners=-,-,- X-VirusChecked: Checked Received: (qmail 36077 invoked from network); 15 Jun 2017 20:31:08 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-5.tower-31.messagelabs.com with SMTP; 15 Jun 2017 20:31:08 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 37CEA15AD; Thu, 15 Jun 2017 13:31:08 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6FE6F3F3E1; Thu, 15 Jun 2017 13:31:07 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 15 Jun 2017 21:30:56 +0100 Message-Id: <20170615203057.755-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170615203057.755-1-julien.grall@arm.com> References: <20170615203057.755-1-julien.grall@arm.com> Cc: proskurin@sec.in.tum.de, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 1/2] xen/arm: Move LPAE definition in a separate header X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" page.h is getting bigger. Move out every LPAE definitions in a separate header. There is no functional changes. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/include/asm-arm/lpae.h | 169 +++++++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/page.h | 152 +--------------------------------------- 2 files changed, 170 insertions(+), 151 deletions(-) create mode 100644 xen/include/asm-arm/lpae.h diff --git a/xen/include/asm-arm/lpae.h b/xen/include/asm-arm/lpae.h new file mode 100644 index 0000000000..1e6a68926e --- /dev/null +++ b/xen/include/asm-arm/lpae.h @@ -0,0 +1,169 @@ +#ifndef __ARM_LPAE_H__ +#define __ARM_LPAE_H__ + +#ifndef __ASSEMBLY__ + +/* WARNING! Unlike the Intel pagetable code, where l1 is the lowest + * level and l4 is the root of the trie, the ARM pagetables follow ARM's + * documentation: the levels are called first, second &c in the order + * that the MMU walks them (i.e. "first" is the root of the trie). */ + +/****************************************************************************** + * ARMv7-A LPAE pagetables: 3-level trie, mapping 40-bit input to + * 40-bit output addresses. Tables at all levels have 512 64-bit entries + * (i.e. are 4Kb long). + * + * The bit-shuffling that has the permission bits in branch nodes in a + * different place from those in leaf nodes seems to be to allow linear + * pagetable tricks. If we're not doing that then the set of permission + * bits that's not in use in a given node type can be used as + * extra software-defined bits. */ + +typedef struct __packed { + /* These are used in all kinds of entry. */ + unsigned long valid:1; /* Valid mapping */ + unsigned long table:1; /* == 1 in 4k map entries too */ + + /* These ten bits are only used in Block entries and are ignored + * in Table entries. */ + unsigned long ai:3; /* Attribute Index */ + unsigned long ns:1; /* Not-Secure */ + unsigned long user:1; /* User-visible */ + unsigned long ro:1; /* Read-Only */ + unsigned long sh:2; /* Shareability */ + unsigned long af:1; /* Access Flag */ + unsigned long ng:1; /* Not-Global */ + + /* The base address must be appropriately aligned for Block entries */ + unsigned long long base:36; /* Base address of block or next table */ + unsigned long sbz:4; /* Must be zero */ + + /* These seven bits are only used in Block entries and are ignored + * in Table entries. */ + unsigned long contig:1; /* In a block of 16 contiguous entries */ + unsigned long pxn:1; /* Privileged-XN */ + unsigned long xn:1; /* eXecute-Never */ + unsigned long avail:4; /* Ignored by hardware */ + + /* These 5 bits are only used in Table entries and are ignored in + * Block entries */ + unsigned long pxnt:1; /* Privileged-XN */ + unsigned long xnt:1; /* eXecute-Never */ + unsigned long apt:2; /* Access Permissions */ + unsigned long nst:1; /* Not-Secure */ +} lpae_pt_t; + +/* The p2m tables have almost the same layout, but some of the permission + * and cache-control bits are laid out differently (or missing) */ +typedef struct __packed { + /* These are used in all kinds of entry. */ + unsigned long valid:1; /* Valid mapping */ + unsigned long table:1; /* == 1 in 4k map entries too */ + + /* These ten bits are only used in Block entries and are ignored + * in Table entries. */ + unsigned long mattr:4; /* Memory Attributes */ + unsigned long read:1; /* Read access */ + unsigned long write:1; /* Write access */ + unsigned long sh:2; /* Shareability */ + unsigned long af:1; /* Access Flag */ + unsigned long sbz4:1; + + /* The base address must be appropriately aligned for Block entries */ + unsigned long long base:36; /* Base address of block or next table */ + unsigned long sbz3:4; + + /* These seven bits are only used in Block entries and are ignored + * in Table entries. */ + unsigned long contig:1; /* In a block of 16 contiguous entries */ + unsigned long sbz2:1; + unsigned long xn:1; /* eXecute-Never */ + unsigned long type:4; /* Ignore by hardware. Used to store p2m types */ + + unsigned long sbz1:5; +} lpae_p2m_t; + +/* Permission mask: xn, write, read */ +#define P2M_PERM_MASK (0x00400000000000C0ULL) +#define P2M_CLEAR_PERM(pte) ((pte).bits & ~P2M_PERM_MASK) + +/* + * Walk is the common bits of p2m and pt entries which are needed to + * simply walk the table (e.g. for debug). + */ +typedef struct __packed { + /* These are used in all kinds of entry. */ + unsigned long valid:1; /* Valid mapping */ + unsigned long table:1; /* == 1 in 4k map entries too */ + + unsigned long pad2:10; + + /* The base address must be appropriately aligned for Block entries */ + unsigned long long base:36; /* Base address of block or next table */ + + unsigned long pad1:16; +} lpae_walk_t; + +typedef union { + uint64_t bits; + lpae_pt_t pt; + lpae_p2m_t p2m; + lpae_walk_t walk; +} lpae_t; + +/* + * These numbers add up to a 48-bit input address space. + * + * On 32-bit the zeroeth level does not exist, therefore the total is + * 39-bits. The ARMv7-A architecture actually specifies a 40-bit input + * address space for the p2m, with an 8K (1024-entry) top-level table. + * However Xen only supports 16GB of RAM on 32-bit ARM systems and + * therefore 39-bits are sufficient. + */ + +#endif /* __ASSEMBLY__ */ + +#define LPAE_SHIFT 9 +#define LPAE_ENTRIES (_AC(1,U) << LPAE_SHIFT) +#define LPAE_ENTRY_MASK (LPAE_ENTRIES - 1) + +#define THIRD_SHIFT (PAGE_SHIFT) +#define THIRD_ORDER (THIRD_SHIFT - PAGE_SHIFT) +#define THIRD_SIZE ((paddr_t)1 << THIRD_SHIFT) +#define THIRD_MASK (~(THIRD_SIZE - 1)) +#define SECOND_SHIFT (THIRD_SHIFT + LPAE_SHIFT) +#define SECOND_ORDER (SECOND_SHIFT - PAGE_SHIFT) +#define SECOND_SIZE ((paddr_t)1 << SECOND_SHIFT) +#define SECOND_MASK (~(SECOND_SIZE - 1)) +#define FIRST_SHIFT (SECOND_SHIFT + LPAE_SHIFT) +#define FIRST_ORDER (FIRST_SHIFT - PAGE_SHIFT) +#define FIRST_SIZE ((paddr_t)1 << FIRST_SHIFT) +#define FIRST_MASK (~(FIRST_SIZE - 1)) +#define ZEROETH_SHIFT (FIRST_SHIFT + LPAE_SHIFT) +#define ZEROETH_ORDER (ZEROETH_SHIFT - PAGE_SHIFT) +#define ZEROETH_SIZE ((paddr_t)1 << ZEROETH_SHIFT) +#define ZEROETH_MASK (~(ZEROETH_SIZE - 1)) + +/* Calculate the offsets into the pagetables for a given VA */ +#define zeroeth_linear_offset(va) ((va) >> ZEROETH_SHIFT) +#define first_linear_offset(va) ((va) >> FIRST_SHIFT) +#define second_linear_offset(va) ((va) >> SECOND_SHIFT) +#define third_linear_offset(va) ((va) >> THIRD_SHIFT) + +#define TABLE_OFFSET(offs) ((unsigned int)(offs) & LPAE_ENTRY_MASK) +#define first_table_offset(va) TABLE_OFFSET(first_linear_offset(va)) +#define second_table_offset(va) TABLE_OFFSET(second_linear_offset(va)) +#define third_table_offset(va) TABLE_OFFSET(third_linear_offset(va)) +#define zeroeth_table_offset(va) TABLE_OFFSET(zeroeth_linear_offset(va)) + +#endif /* __ARM_LPAE_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 6203452387..201da8309a 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -3,6 +3,7 @@ #include #include +#include #ifdef CONFIG_ARM_64 #define PADDR_BITS 48 @@ -101,114 +102,6 @@ #include #include -/* WARNING! Unlike the Intel pagetable code, where l1 is the lowest - * level and l4 is the root of the trie, the ARM pagetables follow ARM's - * documentation: the levels are called first, second &c in the order - * that the MMU walks them (i.e. "first" is the root of the trie). */ - -/****************************************************************************** - * ARMv7-A LPAE pagetables: 3-level trie, mapping 40-bit input to - * 40-bit output addresses. Tables at all levels have 512 64-bit entries - * (i.e. are 4Kb long). - * - * The bit-shuffling that has the permission bits in branch nodes in a - * different place from those in leaf nodes seems to be to allow linear - * pagetable tricks. If we're not doing that then the set of permission - * bits that's not in use in a given node type can be used as - * extra software-defined bits. */ - -typedef struct __packed { - /* These are used in all kinds of entry. */ - unsigned long valid:1; /* Valid mapping */ - unsigned long table:1; /* == 1 in 4k map entries too */ - - /* These ten bits are only used in Block entries and are ignored - * in Table entries. */ - unsigned long ai:3; /* Attribute Index */ - unsigned long ns:1; /* Not-Secure */ - unsigned long user:1; /* User-visible */ - unsigned long ro:1; /* Read-Only */ - unsigned long sh:2; /* Shareability */ - unsigned long af:1; /* Access Flag */ - unsigned long ng:1; /* Not-Global */ - - /* The base address must be appropriately aligned for Block entries */ - unsigned long long base:36; /* Base address of block or next table */ - unsigned long sbz:4; /* Must be zero */ - - /* These seven bits are only used in Block entries and are ignored - * in Table entries. */ - unsigned long contig:1; /* In a block of 16 contiguous entries */ - unsigned long pxn:1; /* Privileged-XN */ - unsigned long xn:1; /* eXecute-Never */ - unsigned long avail:4; /* Ignored by hardware */ - - /* These 5 bits are only used in Table entries and are ignored in - * Block entries */ - unsigned long pxnt:1; /* Privileged-XN */ - unsigned long xnt:1; /* eXecute-Never */ - unsigned long apt:2; /* Access Permissions */ - unsigned long nst:1; /* Not-Secure */ -} lpae_pt_t; - -/* The p2m tables have almost the same layout, but some of the permission - * and cache-control bits are laid out differently (or missing) */ -typedef struct __packed { - /* These are used in all kinds of entry. */ - unsigned long valid:1; /* Valid mapping */ - unsigned long table:1; /* == 1 in 4k map entries too */ - - /* These ten bits are only used in Block entries and are ignored - * in Table entries. */ - unsigned long mattr:4; /* Memory Attributes */ - unsigned long read:1; /* Read access */ - unsigned long write:1; /* Write access */ - unsigned long sh:2; /* Shareability */ - unsigned long af:1; /* Access Flag */ - unsigned long sbz4:1; - - /* The base address must be appropriately aligned for Block entries */ - unsigned long long base:36; /* Base address of block or next table */ - unsigned long sbz3:4; - - /* These seven bits are only used in Block entries and are ignored - * in Table entries. */ - unsigned long contig:1; /* In a block of 16 contiguous entries */ - unsigned long sbz2:1; - unsigned long xn:1; /* eXecute-Never */ - unsigned long type:4; /* Ignore by hardware. Used to store p2m types */ - - unsigned long sbz1:5; -} lpae_p2m_t; - -/* Permission mask: xn, write, read */ -#define P2M_PERM_MASK (0x00400000000000C0ULL) -#define P2M_CLEAR_PERM(pte) ((pte).bits & ~P2M_PERM_MASK) - -/* - * Walk is the common bits of p2m and pt entries which are needed to - * simply walk the table (e.g. for debug). - */ -typedef struct __packed { - /* These are used in all kinds of entry. */ - unsigned long valid:1; /* Valid mapping */ - unsigned long table:1; /* == 1 in 4k map entries too */ - - unsigned long pad2:10; - - /* The base address must be appropriately aligned for Block entries */ - unsigned long long base:36; /* Base address of block or next table */ - - unsigned long pad1:16; -} lpae_walk_t; - -typedef union { - uint64_t bits; - lpae_pt_t pt; - lpae_p2m_t p2m; - lpae_walk_t walk; -} lpae_t; - #if defined(CONFIG_ARM_32) # include #elif defined(CONFIG_ARM_64) @@ -394,49 +287,6 @@ static inline int gva_to_ipa(vaddr_t va, paddr_t *paddr, unsigned int flags) #endif /* __ASSEMBLY__ */ -/* - * These numbers add up to a 48-bit input address space. - * - * On 32-bit the zeroeth level does not exist, therefore the total is - * 39-bits. The ARMv7-A architecture actually specifies a 40-bit input - * address space for the p2m, with an 8K (1024-entry) top-level table. - * However Xen only supports 16GB of RAM on 32-bit ARM systems and - * therefore 39-bits are sufficient. - */ - -#define LPAE_SHIFT 9 -#define LPAE_ENTRIES (_AC(1,U) << LPAE_SHIFT) -#define LPAE_ENTRY_MASK (LPAE_ENTRIES - 1) - -#define THIRD_SHIFT (PAGE_SHIFT) -#define THIRD_ORDER (THIRD_SHIFT - PAGE_SHIFT) -#define THIRD_SIZE ((paddr_t)1 << THIRD_SHIFT) -#define THIRD_MASK (~(THIRD_SIZE - 1)) -#define SECOND_SHIFT (THIRD_SHIFT + LPAE_SHIFT) -#define SECOND_ORDER (SECOND_SHIFT - PAGE_SHIFT) -#define SECOND_SIZE ((paddr_t)1 << SECOND_SHIFT) -#define SECOND_MASK (~(SECOND_SIZE - 1)) -#define FIRST_SHIFT (SECOND_SHIFT + LPAE_SHIFT) -#define FIRST_ORDER (FIRST_SHIFT - PAGE_SHIFT) -#define FIRST_SIZE ((paddr_t)1 << FIRST_SHIFT) -#define FIRST_MASK (~(FIRST_SIZE - 1)) -#define ZEROETH_SHIFT (FIRST_SHIFT + LPAE_SHIFT) -#define ZEROETH_ORDER (ZEROETH_SHIFT - PAGE_SHIFT) -#define ZEROETH_SIZE ((paddr_t)1 << ZEROETH_SHIFT) -#define ZEROETH_MASK (~(ZEROETH_SIZE - 1)) - -/* Calculate the offsets into the pagetables for a given VA */ -#define zeroeth_linear_offset(va) ((va) >> ZEROETH_SHIFT) -#define first_linear_offset(va) ((va) >> FIRST_SHIFT) -#define second_linear_offset(va) ((va) >> SECOND_SHIFT) -#define third_linear_offset(va) ((va) >> THIRD_SHIFT) - -#define TABLE_OFFSET(offs) ((unsigned int)(offs) & LPAE_ENTRY_MASK) -#define first_table_offset(va) TABLE_OFFSET(first_linear_offset(va)) -#define second_table_offset(va) TABLE_OFFSET(second_linear_offset(va)) -#define third_table_offset(va) TABLE_OFFSET(third_linear_offset(va)) -#define zeroeth_table_offset(va) TABLE_OFFSET(zeroeth_linear_offset(va)) - #define PAGE_ALIGN(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK) #endif /* __ARM_PAGE_H__ */