From patchwork Fri Sep 22 08:23:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupinder Thakur X-Patchwork-Id: 113993 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp3011375qgf; Fri, 22 Sep 2017 01:26:19 -0700 (PDT) X-Received: by 10.107.131.77 with SMTP id f74mr6353098iod.215.1506068779863; Fri, 22 Sep 2017 01:26:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506068779; cv=none; d=google.com; s=arc-20160816; b=1JmVI5lPhRM9P/mUhrDt39rhtTuhQzZi57cdr9/RDS4sUdUnXzAUmoX+TRaS+BvytR Q+d9aA+Faux/ML716A+34e5YJpA95JNkDMrQGv79jAMqWPGIV2iCPPseXZIm4FZP1uCQ Sg+oT6ORyJmcUNSonCAGKka0cUgqZ8IHiiA3xBEtxz+A2C3xOh33Uw0AWbCUpMt8zKKE N+sg6E8EqnfPzKyN0zoQ6hvkQ7pK/AGTGIp2DZ/fUjX//HRzi22UboShm2O1Zy6xyMn8 rfP2xQsIA2S9vv56mYOQRMcpA6WWxbc1mQ0Va3oRhNNsZU78hNFcQt9WhCljgqQYZJu4 R2Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=x80X3cVOF2GtV72izfuKrNXUD0dopJtWWYJ3ZCBIDco=; b=URc9yyEEXPZI1kjq6PDQ0T1fsy//peGStlvdj5MRqxxWL3n8vLkgHBEQbVKo0Yc8MR NdKEFznqb/Or/dtUywwR2vVSZacqv+eXaWZF8gq+DZYKNSertf/0z26gdMMc3bLZrJXq 1AgbZeXVxn2YVCRAzRZRTtkwkmMoIS1JL9F9eYXi5FVaa3XBD2K27h2KJAwTv1L3tIJf ThlZ0INNTfddDx5+VlHH0mN3xrtdhu+0KHbjkr6q66TRkskuZqih3H2Pyq/QnPp+NmgC y7lOGdvdHp3YNCV2BuOIPcFBAeQ3r1eC1Z+GsKRUxbMBDwwPyrq8S+vUuejNuaTL7ov0 gNiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UknzJ/Zr; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id s71si3503133itb.75.2017.09.22.01.26.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Sep 2017 01:26:19 -0700 (PDT) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UknzJ/Zr; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dvJGe-000589-WD; Fri, 22 Sep 2017 08:25:00 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1dvJGe-000577-Nn for xen-devel@lists.xenproject.org; Fri, 22 Sep 2017 08:25:00 +0000 Received: from [85.158.143.35] by server-5.bemta-6.messagelabs.com id EB/6C-03454-BD8C4C95; Fri, 22 Sep 2017 08:24:59 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRWlGSWpSXmKPExsXiVRusrXvjxJF Igze7hCy+b5nM5MDocfjDFZYAxijWzLyk/IoE1owd/4ULLllXLLu5gKWB8bV2FyMnh5DAVEaJ Zxvyuxi5OFgE5jFLbD56gAXEkRDoZ5VY+fgVM0iVhECeRMuRXnYIO02i/ex5oDgHkF0hseCnE 8QgLYmjp2azgvQKCexgklgzsZ0JpIZNwERiVocESI2IgJLEvVWTmUBsZoF6iW3nfjGC2MIC+R KHPjwCs1kEVCVe/l3EAmLzCvhINE6fyASxVk7i5rlOsHM4geJr/29ggdjrLbH1xlWWCYyCCxg ZVjGqF6cWlaUW6VroJRVlpmeU5CZm5ugaGpjp5aYWFyemp+YkJhXrJefnbmIEhhoDEOxgnH3Z /xCjJAeTkijv4yNHIoX4kvJTKjMSizPii0pzUosPMcpwcChJ8O48DpQTLEpNT61Iy8wBBj1MW oKDR0mENxwkzVtckJhbnJkOkTrFaMmxb8+tP0wcK67fBpIdN+/+YRJiycvPS5US550P0iAA0p BRmgc3DhaZlxhlpYR5GYEOFOIpSC3KzSxBlX/FKM7BqCTMOwtkCk9mXgnc1ldABzEBHVS+Guy gkkSElFQDY2f8it1bXCpvmv5QmCLqxXEi62OD6+91GW81RZaf44/3n2Scmqy1MHfdheWFK6r7 pxS7xN4sa5vR9euZ7p4zDYYFm2cZdrSem7nq9ar3OUm1TorXnZ4IrLj4RHIm//md1hIM5sdMF IxmMxp9Sbo7ozKeO8LTQaG2OLXvcOTe5OnWVa4H1jCtVGIpzkg01GIuKk4EAJh8POfHAgAA X-Env-Sender: bhupinder.thakur@linaro.org X-Msg-Ref: server-14.tower-21.messagelabs.com!1506068695!77432598!1 X-Originating-IP: [74.125.83.43] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 9.4.45; banners=-,-,- X-VirusChecked: Checked Received: (qmail 30530 invoked from network); 22 Sep 2017 08:24:56 -0000 Received: from mail-pg0-f43.google.com (HELO mail-pg0-f43.google.com) (74.125.83.43) by server-14.tower-21.messagelabs.com with AES128-GCM-SHA256 encrypted SMTP; 22 Sep 2017 08:24:56 -0000 Received: by mail-pg0-f43.google.com with SMTP id 7so239736pgd.13 for ; Fri, 22 Sep 2017 01:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ShLFdjyBwOXeMOQr3lQ1MFu6ReaYVbjCfilIir6inKk=; b=UknzJ/Zr3Lv5W7sfQAEulo9lESiXRn1JFf7zCDsJL9/lrD89JRbQAK5iylKqd0kivQ Hf1FCfbIdh25rbZ207H+MxqtUpzqXFGf8F9JknfXXNjTcK36FSyCgmn2W349oogTFN6n nt4mktNP2bNlLbuf4JMj43u7fNzqFfI54RZrg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ShLFdjyBwOXeMOQr3lQ1MFu6ReaYVbjCfilIir6inKk=; b=BN1+UuRo42InaY8iD1H9adV1HF4RoNRC4tGwAYsIxE1+6irtDfF3NkaZSqQ7Jy1Uxd mwSzSS787434UdAeh08jBpoXt3bvTPR8vfKwnaAUETROpLA9EJGhohM3+1Jputt5YVry YdWaOv6iUjhsbqmr+gQCsbf9FCQlS7qtzgupGO6HEqA+MppxBZCcYhWVdYwBkEQKUsYK FDdULpCGqXf9wLEQ1xKD6pSJvYm8LFv07ax7Pp9lQqt550dwPYijtlWxHWkr2xZtCuEe NiahZHKV/Yor3yYZlr9KBJROkSjjoA3mKnQSBZURWItQ+q7ocp00FgbOJqbIfYUzPpB3 ykeA== X-Gm-Message-State: AHPjjUgTq5lau3j/AQ9hL7f1EF+G3pLMHxC1NSOAPQbqgbhnrrSy6M17 uiVUNr/hGmitTbZfm5JRhTJIfY4Yt7Q= X-Google-Smtp-Source: AOwi7QCFENWuKUvOFjczE3xBH6rHXBv+f9H6yMscTglsUUxJI63JVCzAsn18jcLM5UGPuWnl2cvubA== X-Received: by 10.84.129.226 with SMTP id b89mr8044192plb.6.1506068694402; Fri, 22 Sep 2017 01:24:54 -0700 (PDT) Received: from blr-ubuntu-linaro.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id f74sm5569284pfa.36.2017.09.22.01.24.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 Sep 2017 01:24:54 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Fri, 22 Sep 2017 13:53:26 +0530 Message-Id: <1506068606-17066-28-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506068606-17066-1-git-send-email-bhupinder.thakur@linaro.org> References: <1506068606-17066-1-git-send-email-bhupinder.thakur@linaro.org> Cc: Andre Przywara , Julien Grall , Stefano Stabellini Subject: [Xen-devel] [PATCH 27/27 v10] xen/arm: vpl011: Correct the logic for asserting/de-asserting SBSA UART TX interrupt X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" This patch fixes the issue observed when pl011 patches were tested on the junos hardware by Andre/Julien. It was observed that when large output is generated such as on running 'find /', output was getting truncated intermittently due to OUT ring buffer getting full. This issue was due to the fact that the SBSA UART driver expects that when a TX interrupt is asserted then the FIFO queue should be atleast half empty and that it can write N bytes in the FIFO, where N is half the FIFO queue size, without the bytes getting dropped due to FIFO getting full. The SBSA UART emulation logic was asserting the TX interrupt as soon as any space became available in the FIFO and the SBSA UART driver tried to write more data (upto 16 bytes) in the FIFO expecting that there is enough space available leading to dropped bytes. The SBSA spec [1] does not specify when the TX interrupt should be asserted or de-asserted. Due to lack of clarity on the expected behavior, it is assumed for now that TX interrupt should be asserted only when the FIFO goes half empty. TBD: Once the SBSA spec is updated with the expected behavior, the implementation will be modified to align with the spec requirement. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0183f/DDI0183.pdf Signed-off-by: Bhupinder Thakur --- CC: Julien Grall CC: Andre Przywara CC: Stefano Stabellini Changes since v8: - Used variables fifo_level/fifo_threshold for more clarity - Added a new macro SBSA_UART_FIFO_SIZE instead of using a magic number - Renamed ring_qsize variables to fifo_level for consistency xen/arch/arm/vpl011.c | 87 ++++++++++++++++++++++++++++++-------------- xen/include/asm-arm/vpl011.h | 2 + 2 files changed, 61 insertions(+), 28 deletions(-) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 36794d8..1f97261 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -91,20 +91,24 @@ static uint8_t vpl011_read_data(struct domain *d) */ if ( xencons_queued(in_prod, in_cons, sizeof(intf->in)) > 0 ) { + unsigned int fifo_level; + data = intf->in[xencons_mask(in_cons, sizeof(intf->in))]; in_cons += 1; smp_mb(); intf->in_cons = in_cons; + + fifo_level = xencons_queued(in_prod, in_cons, sizeof(intf->in)); + + if ( fifo_level == 0 ) + { + vpl011->uartfr |= RXFE; + vpl011->uartris &= ~RXI; + } } else gprintk(XENLOG_ERR, "vpl011: Unexpected IN ring buffer empty\n"); - if ( xencons_queued(in_prod, in_cons, sizeof(intf->in)) == 0 ) - { - vpl011->uartfr |= RXFE; - vpl011->uartris &= ~RXI; - } - vpl011->uartfr &= ~RXFF; vpl011_update_interrupt_status(d); @@ -144,28 +148,41 @@ static void vpl011_write_data(struct domain *d, uint8_t data) if ( xencons_queued(out_prod, out_cons, sizeof(intf->out)) != sizeof (intf->out) ) { + unsigned int fifo_level, fifo_threshold; + intf->out[xencons_mask(out_prod, sizeof(intf->out))] = data; out_prod += 1; smp_wmb(); intf->out_prod = out_prod; - } - else - gprintk(XENLOG_ERR, "vpl011: Unexpected OUT ring buffer full\n"); - if ( xencons_queued(out_prod, out_cons, sizeof(intf->out)) == - sizeof (intf->out) ) - { - vpl011->uartfr |= TXFF; - vpl011->uartris &= ~TXI; + fifo_level = xencons_queued(out_prod, out_cons, sizeof(intf->out)); + + if ( fifo_level == sizeof (intf->out) ) + { + vpl011->uartfr |= TXFF; + + /* + * This bit is set only when FIFO becomes full. This ensures that + * the SBSA UART driver can write the early console data as fast as + * possible, without waiting for the BUSY bit to get cleared before + * writing each byte. + */ + vpl011->uartfr |= BUSY; + } /* - * This bit is set only when FIFO becomes full. This ensures that - * the SBSA UART driver can write the early console data as fast as - * possible, without waiting for the BUSY bit to get cleared before - * writing each byte. + * Clear the TXI bit if the fifo level exceeds fifo_size/2 mark which + * is the trigger level for asserting/de-assterting the TX interrupt. */ - vpl011->uartfr |= BUSY; + fifo_threshold = sizeof (intf->out) - SBSA_UART_FIFO_SIZE/2; + + if ( fifo_level <= fifo_threshold ) + vpl011->uartris |= TXI; + else + vpl011->uartris &= ~TXI; } + else + gprintk(XENLOG_ERR, "vpl011: Unexpected OUT ring buffer full\n"); vpl011->uartfr &= ~TXFE; @@ -342,7 +359,7 @@ static void vpl011_data_avail(struct domain *d) struct vpl011 *vpl011 = &d->arch.vpl011; struct xencons_interface *intf = vpl011->ring_buf; XENCONS_RING_IDX in_cons, in_prod, out_cons, out_prod; - XENCONS_RING_IDX in_ring_qsize, out_ring_qsize; + XENCONS_RING_IDX in_fifo_level, out_fifo_level; VPL011_LOCK(d, flags); @@ -353,37 +370,51 @@ static void vpl011_data_avail(struct domain *d) smp_rmb(); - in_ring_qsize = xencons_queued(in_prod, + in_fifo_level = xencons_queued(in_prod, in_cons, sizeof(intf->in)); - out_ring_qsize = xencons_queued(out_prod, + out_fifo_level = xencons_queued(out_prod, out_cons, sizeof(intf->out)); /* Update the uart rx state if the buffer is not empty. */ - if ( in_ring_qsize != 0 ) + if ( in_fifo_level != 0 ) { vpl011->uartfr &= ~RXFE; - if ( in_ring_qsize == sizeof(intf->in) ) + + if ( in_fifo_level == sizeof(intf->in) ) vpl011->uartfr |= RXFF; + vpl011->uartris |= RXI; } /* Update the uart tx state if the buffer is not full. */ - if ( out_ring_qsize != sizeof(intf->out) ) + if ( out_fifo_level != sizeof(intf->out) ) { + unsigned int out_fifo_threshold; + vpl011->uartfr &= ~TXFF; - vpl011->uartris |= TXI; /* - * Clear the BUSY bit as soon as space becomes available + * Clear the BUSY bit as soon as space becomes avaliable * so that the SBSA UART driver can start writing more data * without any further delay. */ vpl011->uartfr &= ~BUSY; - if ( out_ring_qsize == 0 ) + /* + * Set the TXI bit only when there is space for fifo_size/2 bytes which + * is the trigger level for asserting/de-assterting the TX interrupt. + */ + out_fifo_threshold = sizeof(intf->out) - SBSA_UART_FIFO_SIZE/2; + + if ( out_fifo_level <= out_fifo_threshold ) + vpl011->uartris |= TXI; + else + vpl011->uartris &= ~TXI; + + if ( out_fifo_level == 0 ) vpl011->uartfr |= TXFE; } diff --git a/xen/include/asm-arm/vpl011.h b/xen/include/asm-arm/vpl011.h index 1b583da..db95ff8 100644 --- a/xen/include/asm-arm/vpl011.h +++ b/xen/include/asm-arm/vpl011.h @@ -28,6 +28,8 @@ #define VPL011_LOCK(d,flags) spin_lock_irqsave(&(d)->arch.vpl011.lock, flags) #define VPL011_UNLOCK(d,flags) spin_unlock_irqrestore(&(d)->arch.vpl011.lock, flags) +#define SBSA_UART_FIFO_SIZE 32 + struct vpl011 { void *ring_buf; struct page_info *ring_page;