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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id f74sm5569284pfa.36.2017.09.22.01.24.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 Sep 2017 01:24:51 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Fri, 22 Sep 2017 13:53:25 +0530 Message-Id: <1506068606-17066-27-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506068606-17066-1-git-send-email-bhupinder.thakur@linaro.org> References: <1506068606-17066-1-git-send-email-bhupinder.thakur@linaro.org> Cc: Andre Przywara , Julien Grall , Stefano Stabellini Subject: [Xen-devel] [PATCH 26/27 v10] xen/arm: vpl011: Fix the slow early console SBSA UART output X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The early console output uses pl011_early_write() to write data. This function waits for BUSY bit to get cleared before writing the next byte. In the SBSA UART emulation logic, the BUSY bit was set as soon one byte was written in the FIFO and it remained set until the FIFO was emptied. This meant that the output was delayed as each character needed the BUSY to get cleared. Since the SBSA UART is getting emulated in Xen using ring buffers, it ensures that once the data is enqueued in the FIFO, it will be received by xenconsole so it is safe to set the BUSY bit only when FIFO becomes full. This will ensure that pl011_early_write() is not delayed unduly to write the data. Signed-off-by: Bhupinder Thakur --- CC: Julien Grall CC: Andre Przywara CC: Stefano Stabellini xen/arch/arm/vpl011.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 56d9cbe..36794d8 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -157,9 +157,15 @@ static void vpl011_write_data(struct domain *d, uint8_t data) { vpl011->uartfr |= TXFF; vpl011->uartris &= ~TXI; - } - vpl011->uartfr |= BUSY; + /* + * This bit is set only when FIFO becomes full. This ensures that + * the SBSA UART driver can write the early console data as fast as + * possible, without waiting for the BUSY bit to get cleared before + * writing each byte. + */ + vpl011->uartfr |= BUSY; + } vpl011->uartfr &= ~TXFE; @@ -369,11 +375,16 @@ static void vpl011_data_avail(struct domain *d) { vpl011->uartfr &= ~TXFF; vpl011->uartris |= TXI; + + /* + * Clear the BUSY bit as soon as space becomes available + * so that the SBSA UART driver can start writing more data + * without any further delay. + */ + vpl011->uartfr &= ~BUSY; + if ( out_ring_qsize == 0 ) - { - vpl011->uartfr &= ~BUSY; vpl011->uartfr |= TXFE; - } } vpl011_update_interrupt_status(d);