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([185.25.64.249]) by mx.google.com with ESMTPSA id x18sm3518503wia.12.2015.01.29.10.26.36 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 29 Jan 2015 10:26:36 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 29 Jan 2015 18:25:36 +0000 Message-Id: <1422555950-31821-2-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> References: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Vijaya.Kumar@caviumnetworks.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v2 01/15] xen/arm: vgic-v3: Correctly set GICD_TYPER.IDbits X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: >From Linux 3.19, the GICv3 drivers is using GICD_TYPER.IDbits to check the validity of the hardware interrupt number. The field IDBits in the register GICD_TYPER is used to know the number of interrupt identifiers (SPI, PPIs, SGIs, LPIs) supported by GIC Stream Protocol Interface. This field contains the number of interrupt identifier bits minus one. Signed-off-by: Julien Grall --- This patch should be backported to Xen 4.5. Without it any Linux kernel > 3.19 won't boot as a Xen domain. I'm wondering if we should add a release note for this bug. Changes in v2: - vgic_num_irqs has been introduced - Drop GICD_TYPE_ID_BITS_MASK - Use get_count_order --- xen/arch/arm/vgic-v3.c | 11 +++++++++++ xen/include/asm-arm/gic_v3_defs.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index bece189..72b22ee 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -679,11 +679,22 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info) vgic_unlock(v); return 1; case GICD_TYPER: + { + /* + * Number of interrupt identifier bits supported by the GIC + * Stream Protocol Interface + */ + unsigned int irq_bits = get_count_order(vgic_num_irqs(v->domain)); + if ( dabt.size != DABT_WORD ) goto bad_width; /* No secure world support for guests. */ *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) | ((v->domain->arch.vgic.nr_spis / 32) & GICD_TYPE_LINES)); + + *r |= (irq_bits - 1) << GICD_TYPE_ID_BITS_SHIFT; + return 1; + } case GICD_STATUSR: /* * Optional, Not implemented for now. diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 13adb53..85a6d79 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -18,6 +18,9 @@ #ifndef __ASM_ARM_GIC_V3_DEFS_H__ #define __ASM_ARM_GIC_V3_DEFS_H__ +/* Additional bits in GICD_TYPER defined by GICv3 */ +#define GICD_TYPE_ID_BITS_SHIFT 19 + /* * Additional registers defined in GIC v3. * Common GICD registers are defined in gic.h