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([185.25.64.249]) by mx.google.com with ESMTPSA id x18sm3518503wia.12.2015.01.29.10.26.48 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 29 Jan 2015 10:26:49 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 29 Jan 2015 18:25:44 +0000 Message-Id: <1422555950-31821-10-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> References: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Vijaya.Kumar@caviumnetworks.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v2 09/15] xen/arm: vgic-v3: Clarify which distributor is used in the common emulation X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The messages in the common emulation doesn't specify which distributor (redistributor or distributor) is used. This make difficult to find the correct registers. Signed-off-by: Julien Grall --- Changes in v2: - Patch added --- xen/arch/arm/vgic-v3.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 378ac82..b59cc49 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -275,8 +275,8 @@ write_ignore_32: return 1; } -static int __vgic_v3_distr_common_mmio_read(struct vcpu *v, mmio_info_t *info, - uint32_t reg) +static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v, + mmio_info_t *info, uint32_t reg) { struct hsr_dabt dabt = info->dabt; struct cpu_user_regs *regs = guest_cpu_user_regs(); @@ -360,15 +360,14 @@ static int __vgic_v3_distr_common_mmio_read(struct vcpu *v, mmio_info_t *info, return 1; default: printk(XENLOG_G_ERR - "%pv: vGICD/vGICR: unhandled read r%d offset %#08x\n", - v, dabt.reg, reg); + "%pv: %s: unhandled read r%d offset %#08x\n", + v, name, dabt.reg, reg); return 0; } bad_width: - printk(XENLOG_G_ERR - "%pv: vGICD/vGICR: bad read width %d r%d offset %#08x\n", - v, dabt.size, dabt.reg, reg); + printk(XENLOG_G_ERR "%pv: %s: bad read width %d r%d offset %#08x\n", + v, name, dabt.size, dabt.reg, reg); domain_crash_synchronous(); return 0; @@ -377,8 +376,8 @@ read_as_zero: return 1; } -static int __vgic_v3_distr_common_mmio_write(struct vcpu *v, mmio_info_t *info, - uint32_t reg) +static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v, + mmio_info_t *info, uint32_t reg) { struct hsr_dabt dabt = info->dabt; struct cpu_user_regs *regs = guest_cpu_user_regs(); @@ -473,15 +472,15 @@ static int __vgic_v3_distr_common_mmio_write(struct vcpu *v, mmio_info_t *info, return 1; default: printk(XENLOG_G_ERR - "%pv: vGICD/vGICR: unhandled write r%d=%"PRIregister" offset %#08x\n", - v, dabt.reg, *r, reg); + "%pv: %s: unhandled write r%d=%"PRIregister" offset %#08x\n", + v, name, dabt.reg, *r, reg); return 0; } bad_width: printk(XENLOG_G_ERR - "%pv: vGICD/vGICR: bad write width %d r%d=%"PRIregister" offset %#08x\n", - v, dabt.size, dabt.reg, *r, reg); + "%pv: %s: bad write width %d r%d=%"PRIregister" offset %#08x\n", + v, name, dabt.size, dabt.reg, *r, reg); domain_crash_synchronous(); return 0; @@ -516,7 +515,8 @@ static int vgic_v3_rdistr_sgi_mmio_read(struct vcpu *v, mmio_info_t *info, * Above registers offset are common with GICD. * So handle in common with GICD handling */ - return __vgic_v3_distr_common_mmio_read(v, info, gicr_reg); + return __vgic_v3_distr_common_mmio_read("vGICR: SGI", v, info, + gicr_reg); case GICR_ISPENDR0: if ( dabt.size != DABT_WORD ) goto bad_width; rank = vgic_rank_offset(v, 1, gicr_reg - GICR_ISPENDR0, DABT_WORD); @@ -581,7 +581,8 @@ static int vgic_v3_rdistr_sgi_mmio_write(struct vcpu *v, mmio_info_t *info, * Above registers offset are common with GICD. * So handle common with GICD handling */ - return __vgic_v3_distr_common_mmio_write(v, info, gicr_reg); + return __vgic_v3_distr_common_mmio_write("vGICR: SGI", v, + info, gicr_reg); case GICR_ISPENDR0: if ( dabt.size != DABT_WORD ) goto bad_width; rank = vgic_rank_offset(v, 1, gicr_reg - GICR_ISACTIVER0, DABT_WORD); @@ -782,7 +783,7 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info) * Above all register are common with GICR and GICD * Manage in common */ - return __vgic_v3_distr_common_mmio_read(v, info, gicd_reg); + return __vgic_v3_distr_common_mmio_read("vGICD", v, info, gicd_reg); case GICD_IROUTER ... GICD_IROUTER31: /* SGI/PPI is RES0 */ goto read_as_zero_64; @@ -947,7 +948,7 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info) case GICD_ICFGR ... GICD_ICFGRN: /* Above registers are common with GICR and GICD * Manage in common */ - return __vgic_v3_distr_common_mmio_write(v, info, gicd_reg); + return __vgic_v3_distr_common_mmio_write("vGICD", v, info, gicd_reg); case GICD_IROUTER ... GICD_IROUTER31: /* SGI/PPI is RES0 */ goto write_ignore_64;