From patchwork Tue Aug 5 11:26:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 34941 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f71.google.com (mail-oa0-f71.google.com [209.85.219.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 03CAA23B13 for ; Tue, 5 Aug 2014 11:29:18 +0000 (UTC) Received: by mail-oa0-f71.google.com with SMTP id g18sf3434683oah.2 for ; Tue, 05 Aug 2014 04:29:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=iYUFjSgm3pv4t/9T+AU1Cx4sg2I+7SPZX2y/hpLkEo4=; b=hUlTN6x/PumtwTs78sLkxZH4OnJv8KxnDb18mLDM8XmCmB1tuGMtEr7PKQ19sThf6V Myhp71Px5cSfD1/u2bKtgVKPPFqhCLgOUOk5md2Eaup6w13KssAB+I26iW/bg0fgn21j vzOhKi2zyRUkeEwpKLRJGoG8BTtUM8UMF5m4l+bmSSHZuWbq33XSjBaGMnoSSqMrnhY5 gxmloMBdT6CJ9SHhyiHvABAEuYyxOwLg8+HbpnvP7oLd0xX32VDUswJvfsrlxb8em0Zm ECIJSffIVqEyXjVY+oQ5HJNIZGT2DqYtj9ERspGVcaqIAxDwH5bmovQtc0nXV1LphYLk 5I7w== X-Gm-Message-State: ALoCoQlqd3zLtN4rQrPS3wNF+7vbwqaPqvs15g508R0hQByws2FypfOHxX0BnfBC1MDw/xt5pFKE X-Received: by 10.50.33.18 with SMTP id n18mr12053036igi.8.1407238158455; Tue, 05 Aug 2014 04:29:18 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.82.167 with SMTP id h36ls230483qgd.77.gmail; Tue, 05 Aug 2014 04:29:18 -0700 (PDT) X-Received: by 10.220.172.134 with SMTP id l6mr85284vcz.80.1407238158310; Tue, 05 Aug 2014 04:29:18 -0700 (PDT) Received: from mail-vc0-f171.google.com (mail-vc0-f171.google.com [209.85.220.171]) by mx.google.com with ESMTPS id s3si833938veg.62.2014.08.05.04.29.18 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 05 Aug 2014 04:29:18 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) client-ip=209.85.220.171; Received: by mail-vc0-f171.google.com with SMTP id hq11so1174415vcb.30 for ; Tue, 05 Aug 2014 04:29:18 -0700 (PDT) X-Received: by 10.221.5.137 with SMTP id og9mr1621243vcb.18.1407238158197; Tue, 05 Aug 2014 04:29:18 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp379318vcb; Tue, 5 Aug 2014 04:29:17 -0700 (PDT) X-Received: by 10.42.166.2 with SMTP id m2mr5006812icy.21.1407238157341; Tue, 05 Aug 2014 04:29:17 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id yd11si3465932icb.21.2014.08.05.04.29.16 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 05 Aug 2014 04:29:17 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XEcuH-0004Zi-Tx; Tue, 05 Aug 2014 11:27:53 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XEcuF-0004XD-3R for xen-devel@lists.xensource.com; Tue, 05 Aug 2014 11:27:51 +0000 Received: from [85.158.143.35:9409] by server-3.bemta-4.messagelabs.com id B6/F1-06192-6BFB0E35; Tue, 05 Aug 2014 11:27:50 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-6.tower-21.messagelabs.com!1407238067!13490174!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 17153 invoked from network); 5 Aug 2014 11:27:49 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-6.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 5 Aug 2014 11:27:49 -0000 X-IronPort-AV: E=Sophos;i="5.01,804,1400025600"; d="scan'208";a="158837271" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.3.181.6; Tue, 5 Aug 2014 07:27:46 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1XEcu5-0002cW-IP; Tue, 05 Aug 2014 12:27:41 +0100 From: Stefano Stabellini To: Date: Tue, 5 Aug 2014 12:26:26 +0100 Message-ID: <1407237989-27654-7-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v10 07/10] xen: remove workaround to inject evtchn_irq on irq enable X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: evtchn_upcall_pending is already set by common code at vcpu creation, therefore on ARM we also need to call vgic_vcpu_inject_irq for it. Currently we do that from vgic_enable_irqs as a workaround. Do this properly by introducing an appropriate arch specific hook: arch_evtchn_inject. arch_evtchn_inject is called by map_vcpu_info to inject the evtchn irq into the guest. On ARM is implemented by calling vgic_vcpu_inject_irq. On x86 guests typically don't call VCPUOP_register_vcpu_info on vcpu0, therefore avoiding the issue. However theoretically they could call VCPUOP_register_vcpu_info on vcpu0 and in that case Xen would need to inject the event channel notification into the guest if the guest is HVM. So implement arch_evtchn_inject on x86 by calling hvm_assert_evtchn_irq. Signed-off-by: Stefano Stabellini Acked-by: Julien Grall --- Changes in v10: - provide an implementation for x86. Changes in v9: - use an arch hook. Changes in v2: - coding style fix; - add comment; - return an error if arch_set_info_guest is called without VGCF_online. --- xen/arch/arm/vgic.c | 23 +++++++++-------------- xen/arch/x86/hvm/irq.c | 6 ++++++ xen/common/domain.c | 1 + xen/include/xen/event.h | 3 +++ 4 files changed, 19 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 731d84d..ce4457e 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -263,20 +263,10 @@ void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) v_target = d->arch.vgic.handler->get_target_vcpu(v, irq); p = irq_to_pending(v_target, irq); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status); - /* We need to force the first injection of evtchn_irq because - * evtchn_upcall_pending is already set by common code on vcpu - * creation. */ - if ( irq == v_target->domain->arch.evtchn_irq && - vcpu_info(current, evtchn_upcall_pending) && - list_empty(&p->inflight) ) - vgic_vcpu_inject_irq(v_target, irq); - else { - unsigned long flags; - spin_lock_irqsave(&v_target->arch.vgic.lock, flags); - if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) - gic_raise_guest_irq(v_target, irq, p->priority); - spin_unlock_irqrestore(&v_target->arch.vgic.lock, flags); - } + spin_lock_irqsave(&v_target->arch.vgic.lock, flags); + if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_raise_guest_irq(v_target, irq, p->priority); + spin_unlock_irqrestore(&v_target->arch.vgic.lock, flags); if ( p->desc != NULL ) { irq_set_affinity(p->desc, cpumask_of(v_target->processor)); @@ -432,6 +422,11 @@ void vgic_vcpu_inject_spi(struct domain *d, unsigned int irq) vgic_vcpu_inject_irq(v, irq); } +void arch_evtchn_inject(struct vcpu *v) +{ + vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); +} + /* * Local variables: * mode: C diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c index 3b29678..35f4f94 100644 --- a/xen/arch/x86/hvm/irq.c +++ b/xen/arch/x86/hvm/irq.c @@ -468,6 +468,12 @@ int hvm_local_events_need_delivery(struct vcpu *v) return !hvm_interrupt_blocked(v, intack); } +void arch_evtchn_inject(struct vcpu *v) +{ + if ( has_hvm_container_vcpu(v) ) + hvm_assert_evtchn_irq(v); +} + static void irq_dump(struct domain *d) { struct hvm_irq *hvm_irq = &d->arch.hvm_domain.irq; diff --git a/xen/common/domain.c b/xen/common/domain.c index cd64aea..05d0049 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1058,6 +1058,7 @@ int map_vcpu_info(struct vcpu *v, unsigned long gfn, unsigned offset) vcpu_info(v, evtchn_upcall_pending) = 1; for ( i = 0; i < BITS_PER_EVTCHN_WORD(d); i++ ) set_bit(i, &vcpu_info(v, evtchn_pending_sel)); + arch_evtchn_inject(v); return 0; } diff --git a/xen/include/xen/event.h b/xen/include/xen/event.h index 06c0654..fe19165 100644 --- a/xen/include/xen/event.h +++ b/xen/include/xen/event.h @@ -69,6 +69,9 @@ int guest_enabled_event(struct vcpu *v, uint32_t virq); /* Notify remote end of a Xen-attached event channel.*/ void notify_via_xen_event_channel(struct domain *ld, int lport); +/* inject an event channel notification into the guest */ +void arch_evtchn_inject(struct vcpu *v); + /* * Internal event channel object storage. *