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[50.57.142.19]) by mx.google.com with ESMTPS id gb4si3434881icb.75.2014.08.05.04.29.17 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 05 Aug 2014 04:29:17 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XEcuI-0004bU-W3; Tue, 05 Aug 2014 11:27:54 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XEcuG-0004YG-3L for xen-devel@lists.xensource.com; Tue, 05 Aug 2014 11:27:52 +0000 Received: from [193.109.254.147:16962] by server-5.bemta-14.messagelabs.com id E4/E7-28255-7BFB0E35; Tue, 05 Aug 2014 11:27:51 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-5.tower-27.messagelabs.com!1407238069!9188767!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 3317 invoked from network); 5 Aug 2014 11:27:50 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-5.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 5 Aug 2014 11:27:50 -0000 X-IronPort-AV: E=Sophos;i="5.01,804,1400025600"; d="scan'208";a="159461797" Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.3.181.6; Tue, 5 Aug 2014 07:27:46 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1XEcu5-0002cW-FU; Tue, 05 Aug 2014 12:27:41 +0100 From: Stefano Stabellini To: Date: Tue, 5 Aug 2014 12:26:23 +0100 Message-ID: <1407237989-27654-4-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v10 04/10] xen/arm: support irq delivery to vcpu > 0 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Use vgic_get_target_vcpu to retrieve the target vcpu from do_IRQ. Remove in-code comments about missing implementation of SGI delivery to vcpus other than 0. Signed-off-by: Stefano Stabellini Acked-by: Julien Grall Acked-by: Ian Campbell --- Changes in v7: - improve in-code comment; - use gic_number_lines in assert. Changes in v6: - add in-code comments; - assert that the guest irq is an SPI. Changes in v4: - the mask in gic_route_irq_to_guest is a physical cpu mask, treat it as such; - export vgic_get_target_vcpu in a previous patch. --- xen/arch/arm/gic.c | 3 ++- xen/arch/arm/irq.c | 5 +++-- xen/arch/arm/vgic.c | 11 +++++++++++ xen/include/asm-arm/vgic.h | 1 + 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 3e75fc5..f5c7c91 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -137,7 +137,8 @@ void gic_route_irq_to_guest(struct domain *d, struct irq_desc *desc, gic_set_irq_properties(desc, cpumask_of(smp_processor_id()), GIC_PRI_IRQ); - /* TODO: do not assume delivery to vcpu0 */ + /* Use vcpu0 to retrieve the pending_irq struct. Given that we only + * route SPIs to guests, it doesn't make any difference. */ p = irq_to_pending(d->vcpu[0], desc->irq); p->desc = desc; } diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 3a8acbf..49ca467 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -198,8 +198,9 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) desc->status |= IRQ_INPROGRESS; desc->arch.eoi_cpu = smp_processor_id(); - /* XXX: inject irq into all guest vcpus */ - vgic_vcpu_inject_irq(d->vcpu[0], irq); + /* the irq cannot be a PPI, we only support delivery of SPIs to + * guests */ + vgic_vcpu_inject_spi(d, irq); goto out_no_end; } diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 9e1dd49..4344c36 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -400,6 +400,17 @@ out: smp_send_event_check_mask(cpumask_of(v->processor)); } +void vgic_vcpu_inject_spi(struct domain *d, unsigned int irq) +{ + struct vcpu *v; + + /* the IRQ needs to be an SPI */ + ASSERT(irq >= 32 && irq <= gic_number_lines()); + + v = vgic_get_target_vcpu(d->vcpu[0], irq); + vgic_vcpu_inject_irq(v, irq); +} + /* * Local variables: * mode: C diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 434a625..9b1db04 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -161,6 +161,7 @@ extern void domain_vgic_free(struct domain *d); extern int vcpu_vgic_init(struct vcpu *v); extern struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int irq); extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq); +extern void vgic_vcpu_inject_spi(struct domain *d, unsigned int irq); extern void vgic_clear_pending_irqs(struct vcpu *v); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, int b, int n, int s);