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[50.57.142.19]) by mx.google.com with ESMTPS id kl7si3981558igb.13.2014.07.25.09.15.56 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 25 Jul 2014 09:15:56 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XAi85-00012H-2u; Fri, 25 Jul 2014 16:13:57 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XAi83-00012A-LK for xen-devel@lists.xen.org; Fri, 25 Jul 2014 16:13:55 +0000 Received: from [193.109.254.147:50257] by server-8.bemta-14.messagelabs.com id 2E/85-07074-34282D35; Fri, 25 Jul 2014 16:13:55 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-6.tower-27.messagelabs.com!1406304833!11817639!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6654 invoked from network); 25 Jul 2014 16:13:54 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-6.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 25 Jul 2014 16:13:54 -0000 X-IronPort-AV: E=Sophos;i="5.01,731,1400025600"; d="scan'208";a="155730637" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 25 Jul 2014 16:13:52 +0000 Received: from kazak.uk.xensource.com (10.80.2.80) by FTLPEX01CL03.citrite.net (10.13.107.80) with Microsoft SMTP Server id 14.3.181.6; Fri, 25 Jul 2014 12:13:52 -0400 Message-ID: <1406304831.24842.54.camel@kazak.uk.xensource.com> From: Ian Campbell To: Julien Grall Date: Fri, 25 Jul 2014 17:13:51 +0100 In-Reply-To: <1406304202.24842.50.camel@kazak.uk.xensource.com> References: <80a33cc325055bc9d63e4ef272c5b7f68f8fa812.1406301772.git.ian.campbell@citrix.com> <2c06427f1180cf408a3e9750de3040dde0afe2ea.1406301772.git.ian.campbell@citrix.com> <53D27AF3.5070706@linaro.org> <1406303283.24842.41.camel@kazak.uk.xensource.com> <53D27C6B.6070907@linaro.org> <1406304202.24842.50.camel@kazak.uk.xensource.com> Organization: Citrix Systems, Inc. X-Mailer: Evolution 3.12.2-1 MIME-Version: 1.0 X-Originating-IP: [10.80.2.80] X-DLP: MIA2 Cc: xen-devel@lists.xen.org, tim@xen.org, stefano.stabellini@eu.citrix.com Subject: Re: [Xen-devel] [PATCH 2/2] xen: arm: update arm32 assembly primitives to Linux v3.16-rc6 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On Fri, 2014-07-25 at 17:03 +0100, Ian Campbell wrote: > On Fri, 2014-07-25 at 16:48 +0100, Julien Grall wrote: > > On 07/25/2014 04:48 PM, Ian Campbell wrote: > > > On Fri, 2014-07-25 at 16:42 +0100, Julien Grall wrote: > > >> Hi Ian, > > >> > > >> On 07/25/2014 04:22 PM, Ian Campbell wrote: > > >>> bitops, cmpxchg, atomics: Import: > > >>> c32ffce ARM: 7984/1: prefetch: add prefetchw invocations for barriered atomics > > >> > > >> Compare to Linux we don't have specific prefetch* helpers. We directly > > >> use the compiler builtin ones. Shouldn't we import the ARM specific > > >> helpers to gain in performance? > > > > > > My binaries are full of pld instructions where I think I would expect > > > them, so it seems like the compiler builtin ones are sufficient. > > > > > > I suspect the Linux define is there to cope with older compilers or > > > something. > > > > If so: > > The compiled output is very different if I use the arch specific > explicit variants. The explicit variant generates (lots) more pldw and > (somewhat) fewer pld. I've no idea what this means... It's a bit more obvious for aarch64 where gcc 4.8 doesn't generate any prefetches at all via the builtins... Here's what I've got in my tree. I've no idea if we should take some or all of it... Ian. 8<----------------- >From feb516fee01a0af60f54337b323975154eb466d8 Mon Sep 17 00:00:00 2001 Message-Id: From: Ian Campbell Date: Fri, 25 Jul 2014 17:08:42 +0100 Subject: [PATCH] xen: arm: Use explicit prefetch instructions. On ARM32 these certainly generate *different* sets of prefetches. I've no clue if that is a good thing... On ARM64 the builtin variants seems to be non-functional (at least with gcc 4.8). Signed-off-by: Ian Campbell --- xen/include/asm-arm/arm32/processor.h | 17 +++++++++++++++++ xen/include/asm-arm/arm64/processor.h | 22 ++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index f41644d..6feacc9 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -119,6 +119,23 @@ struct cpu_user_regs #define cpu_has_erratum_766422() \ (unlikely(current_cpu_data.midr.bits == 0x410fc0f4)) +#define ARCH_HAS_PREFETCH +static inline void prefetch(const void *ptr) +{ + __asm__ __volatile__( + "pld\t%a0" + :: "p" (ptr)); +} + +#define ARCH_HAS_PREFETCHW +static inline void prefetchw(const void *ptr) +{ + __asm__ __volatile__( + ".arch_extension mp\n" + "pldw\t%a0" + :: "p" (ptr)); +} + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM32_PROCESSOR_H */ diff --git a/xen/include/asm-arm/arm64/processor.h b/xen/include/asm-arm/arm64/processor.h index 5bf0867..56b1002 100644 --- a/xen/include/asm-arm/arm64/processor.h +++ b/xen/include/asm-arm/arm64/processor.h @@ -106,6 +106,28 @@ struct cpu_user_regs #define cpu_has_erratum_766422() 0 +/* + * Prefetching support + */ +#define ARCH_HAS_PREFETCH +static inline void prefetch(const void *ptr) +{ + asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr)); +} + +#define ARCH_HAS_PREFETCHW +static inline void prefetchw(const void *ptr) +{ + asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr)); +} + +#define ARCH_HAS_SPINLOCK_PREFETCH +static inline void spin_lock_prefetch(const void *x) +{ + prefetchw(x); +} + + #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARM_ARM64_PROCESSOR_H */