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[50.57.142.19]) by mx.google.com with ESMTPS id qo6si21058835igb.61.2014.07.24.10.36.47 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 24 Jul 2014 10:36:47 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XAMuo-0002Ts-Px; Thu, 24 Jul 2014 17:34:50 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1XAMun-0002Sp-5u for xen-devel@lists.xensource.com; Thu, 24 Jul 2014 17:34:49 +0000 Received: from [85.158.137.68:32654] by server-14.bemta-3.messagelabs.com id F9/BB-09441-8B341D35; Thu, 24 Jul 2014 17:34:48 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-12.tower-31.messagelabs.com!1406223285!17781062!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 30550 invoked from network); 24 Jul 2014 17:34:47 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-12.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 24 Jul 2014 17:34:47 -0000 X-IronPort-AV: E=Sophos;i="5.01,725,1400025600"; d="scan'208";a="155886521" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 24 Jul 2014 17:34:18 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.3.181.6; Thu, 24 Jul 2014 13:34:17 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1XAMuC-00067o-EI; Thu, 24 Jul 2014 18:34:12 +0100 From: Stefano Stabellini To: Date: Thu, 24 Jul 2014 18:33:07 +0100 Message-ID: <1406223192-26267-5-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v9 05/10] xen/arm: physical irq follow virtual irq X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.180 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Migrate physical irqs to the same physical cpu that is running the vcpu expected to receive the irqs. That is done when enabling irqs, when the guest writes to GICD_ITARGETSR and when Xen migrates a vcpu to a different pcpu. In case of virq migration, if the virq is inflight and in a GICH_LR register already, delay migrating the corresponding physical irq until the virq is EOIed by the guest and the MIGRATING flag has been cleared. This way we make sure that the pcpu running the old vcpu gets interrupted with a new irq of the same kind, clearing the GICH_LR sooner. Introduce a new arch specific function, arch_move_irqs, that is empty on x86 and implements the vgic irq migration code on ARM. arch_move_irqs is going to be called by from sched.c. Signed-off-by: Stefano Stabellini Acked-by: Jan Beulich --- Changes in v9: - move arch_move_irqs declaration to irq.h. Changes in v7: - remove checks at the top of gic_irq_set_affinity, add assert instead; - move irq_set_affinity to irq.c; - delay setting the affinity of the physical irq when the virq is MIGRATING until the virq is EOIed by the guest; - do not set the affinity of MIGRATING irqs from arch_move_irqs. Changes in v6: - use vgic_get_target_vcpu instead of _vgic_get_target_vcpu in arch_move_irqs. Changes in v5: - prettify vgic_move_irqs; - rename vgic_move_irqs to arch_move_irqs; - introduce helper function irq_set_affinity. --- xen/arch/arm/gic-v2.c | 15 +++++++++++++-- xen/arch/arm/gic.c | 6 +++++- xen/arch/arm/irq.c | 6 ++++++ xen/arch/arm/vgic.c | 21 +++++++++++++++++++++ xen/include/asm-arm/irq.h | 3 +++ xen/include/asm-x86/irq.h | 2 ++ 6 files changed, 50 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 1305542..da60a41 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -569,9 +569,20 @@ static void gicv2_guest_irq_end(struct irq_desc *desc) /* Deactivation happens in maintenance interrupt / via GICV */ } -static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask) +static void gicv2_irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask) { - BUG(); + unsigned int mask; + + ASSERT(!cpumask_empty(cpu_mask)); + + spin_lock(&gicv2.lock); + + mask = gicv2_cpu_mask(cpu_mask); + + /* Set target CPU mask (RAZ/WI on uniprocessor) */ + writeb_gicd(mask, GICD_ITARGETSR + desc->irq); + + spin_unlock(&gicv2.lock); } /* XXX different for level vs edge */ diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index f5c7c91..2aa9500 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -382,7 +382,11 @@ static void gic_update_one_lr(struct vcpu *v, int i) gic_raise_guest_irq(v, irq, p->priority); else { list_del_init(&p->inflight); - clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status); + if ( test_and_clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) + { + struct vcpu *v_target = vgic_get_target_vcpu(v, irq); + irq_set_affinity(p->desc, cpumask_of(v_target->processor)); + } } } } diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 49ca467..7150c7a 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -134,6 +134,12 @@ static inline struct domain *irq_get_domain(struct irq_desc *desc) return desc->action->dev_id; } +void irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask) +{ + if ( desc != NULL ) + desc->handler->set_affinity(desc, cpu_mask); +} + int request_irq(unsigned int irq, unsigned int irqflags, void (*handler)(int, void *, struct cpu_user_regs *), const char *devname, void *dev_id) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 02e5985..299ae7e 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -182,6 +182,7 @@ void vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq) if ( list_empty(&p->inflight) ) { + irq_set_affinity(p->desc, cpumask_of(new->processor)); spin_unlock_irqrestore(&old->arch.vgic.lock, flags); return; } @@ -190,6 +191,7 @@ void vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq) { list_del_init(&p->lr_queue); list_del_init(&p->inflight); + irq_set_affinity(p->desc, cpumask_of(new->processor)); spin_unlock_irqrestore(&old->arch.vgic.lock, flags); vgic_vcpu_inject_irq(new, irq); return; @@ -202,6 +204,24 @@ void vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq) spin_unlock_irqrestore(&old->arch.vgic.lock, flags); } +void arch_move_irqs(struct vcpu *v) +{ + const cpumask_t *cpu_mask = cpumask_of(v->processor); + struct domain *d = v->domain; + struct pending_irq *p; + struct vcpu *v_target; + int i; + + for ( i = 32; i < d->arch.vgic.nr_lines; i++ ) + { + v_target = vgic_get_target_vcpu(v, i); + p = irq_to_pending(v_target, i); + + if ( v_target == v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) + irq_set_affinity(p->desc, cpu_mask); + } +} + void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) { struct domain *d = v->domain; @@ -259,6 +279,7 @@ void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) } if ( p->desc != NULL ) { + irq_set_affinity(p->desc, cpumask_of(v_target->processor)); spin_lock_irqsave(&p->desc->lock, flags); p->desc->handler->enable(p->desc); spin_unlock_irqrestore(&p->desc->lock, flags); diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index e567f71..e877334 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -42,12 +42,15 @@ void init_secondary_IRQ(void); int route_irq_to_guest(struct domain *d, unsigned int irq, const char *devname); +void arch_move_irqs(struct vcpu *v); /* Set IRQ type for an SPI */ int irq_set_spi_type(unsigned int spi, unsigned int type); int platform_get_irq(const struct dt_device_node *device, int index); +void irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask); + #endif /* _ASM_HW_IRQ_H */ /* * Local variables: diff --git a/xen/include/asm-x86/irq.h b/xen/include/asm-x86/irq.h index 9066d38..d3c55f3 100644 --- a/xen/include/asm-x86/irq.h +++ b/xen/include/asm-x86/irq.h @@ -197,4 +197,6 @@ void cleanup_domain_irq_mapping(struct domain *); bool_t cpu_has_pending_apic_eoi(void); +static inline void arch_move_irqs(struct vcpu *v) { } + #endif /* _ASM_HW_IRQ_H */