From patchwork Tue Jul 22 00:43:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roy Franz X-Patchwork-Id: 34019 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ig0-f200.google.com (mail-ig0-f200.google.com [209.85.213.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 6F67E20492 for ; Tue, 22 Jul 2014 00:46:44 +0000 (UTC) Received: by mail-ig0-f200.google.com with SMTP id uq10sf16785670igb.3 for ; Mon, 21 Jul 2014 17:46:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:cc:subject:precedence:list-id:list-unsubscribe:list-post :list-help:list-subscribe:mime-version:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list :list-archive:content-type:content-transfer-encoding; bh=Rg2BkmYwjKSKEZE4kNcHj907ceOsBOE11AIo+xfHN/U=; b=YclcO3fAG3mSLj2TNTDoGXCNsOn2d0PuysNVAcKGhD6tX/rIwlGjUdKXO8UOD6OWz9 MZgBFSxwOQz+xnW+1Zr2W2SUAHN2877TpLXWzdPJotVQQ8PBalcwe2lpN6gHTRnj2hg7 Ifq+iBEPPkvcurkNbgxCW7nlEOvcJO2IdxlNbZDSShjv+ub3oirMn/jyjK+SIRIQ3TYr MZkSvdXuFXtwJXWIfOKmNtVqi6USnM/z0kIj+3GwYpFkqJRkTCI0ELtGywkDPjhl7ZDn 6FR0llvekdVhN1AAduiqQXbOB5hl8lX7MDD/rcAzOffLRTzh+oXLyJbIwfXIfc6dQp5v yqTQ== X-Gm-Message-State: ALoCoQkU5PM1JnMrq+fybJGiKxpVWqC5KKnA9cxRiyg0X/OkiIfG6teAo0lBJD+4bVnoPOcO+6V2 X-Received: by 10.50.88.105 with SMTP id bf9mr9638694igb.1.1405990004030; Mon, 21 Jul 2014 17:46:44 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.27.171 with SMTP id 40ls2161490qgx.9.gmail; Mon, 21 Jul 2014 17:46:43 -0700 (PDT) X-Received: by 10.52.232.200 with SMTP id tq8mr29609669vdc.32.1405990003843; Mon, 21 Jul 2014 17:46:43 -0700 (PDT) Received: from mail-vc0-f181.google.com (mail-vc0-f181.google.com [209.85.220.181]) by mx.google.com with ESMTPS id yy2si12837883vdc.48.2014.07.21.17.46.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 21 Jul 2014 17:46:43 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) client-ip=209.85.220.181; Received: by mail-vc0-f181.google.com with SMTP id lf12so13559080vcb.40 for ; Mon, 21 Jul 2014 17:46:43 -0700 (PDT) X-Received: by 10.220.50.8 with SMTP id x8mr27774150vcf.18.1405990003744; Mon, 21 Jul 2014 17:46:43 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp154188vcb; Mon, 21 Jul 2014 17:46:43 -0700 (PDT) X-Received: by 10.140.43.245 with SMTP id e108mr44108158qga.76.1405990003284; Mon, 21 Jul 2014 17:46:43 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id w3si16567958qas.67.2014.07.21.17.46.42 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 21 Jul 2014 17:46:43 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X9OBp-0000Db-Eo; Tue, 22 Jul 2014 00:44:21 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X9OBn-0000Bk-IW for xen-devel@lists.xen.org; Tue, 22 Jul 2014 00:44:19 +0000 Received: from [193.109.254.147:30600] by server-6.bemta-14.messagelabs.com id 19/6D-31278-2E3BDC35; Tue, 22 Jul 2014 00:44:18 +0000 X-Env-Sender: roy.franz@linaro.org X-Msg-Ref: server-15.tower-27.messagelabs.com!1405989856!18774519!1 X-Originating-IP: [209.85.220.53] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 11889 invoked from network); 22 Jul 2014 00:44:17 -0000 Received: from mail-pa0-f53.google.com (HELO mail-pa0-f53.google.com) (209.85.220.53) by server-15.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 22 Jul 2014 00:44:17 -0000 Received: by mail-pa0-f53.google.com with SMTP id kq14so10834666pab.40 for ; Mon, 21 Jul 2014 17:44:15 -0700 (PDT) X-Received: by 10.66.234.202 with SMTP id ug10mr13785569pac.109.1405989855712; Mon, 21 Jul 2014 17:44:15 -0700 (PDT) Received: from rfranz-t520.local (c-24-10-97-91.hsd1.ca.comcast.net. [24.10.97.91]) by mx.google.com with ESMTPSA id fl3sm15417298pbc.35.2014.07.21.17.44.14 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Jul 2014 17:44:15 -0700 (PDT) From: Roy Franz To: xen-devel@lists.xen.org, ian.campbell@citrix.com, stefano.stabellini@citrix.com, tim@xen.org, jbeulich@suse.com, keir@xen.org Date: Mon, 21 Jul 2014 17:43:33 -0700 Message-Id: <1405989815-25236-11-git-send-email-roy.franz@linaro.org> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1405989815-25236-1-git-send-email-roy.franz@linaro.org> References: <1405989815-25236-1-git-send-email-roy.franz@linaro.org> Cc: Roy Franz , fu.wei@linaro.org, linaro-uefi@lists.linaro.org Subject: [Xen-devel] [PATCH V2 10/12] add arm64 cache flushing code from linux X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: roy.franz@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: __flush_dcache_all added from arch/arm64/mm/cache.S, with helper macros from arch/arm64/include/asm/assembler.h, both from v3.16-rc6. The cache flushing is required when transitioning from EFI code that runs with cache enable to XEN startup code which expects the cache to be disabled. Signed-off-by: Roy Franz --- xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/cache.S | 100 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 xen/arch/arm/arm64/cache.S diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index d2d5875..c7243f5 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -7,5 +7,6 @@ obj-y += domain.o obj-y += vfp.o obj-y += smpboot.o obj-y += domctl.o +obj-y += cache.o obj-$(EARLY_PRINTK) += debug.o diff --git a/xen/arch/arm/arm64/cache.S b/xen/arch/arm/arm64/cache.S new file mode 100644 index 0000000..2c19adb --- /dev/null +++ b/xen/arch/arm/arm64/cache.S @@ -0,0 +1,100 @@ +/* + * Cache maintenance + * + * Copyright (C) 2001 Deep Blue Solutions Ltd. + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Enable and disable interrupts. + */ + .macro disable_irq + msr daifset, #2 + .endm + + .macro enable_irq + msr daifclr, #2 + .endm + +/* + * Save/disable and restore interrupts. + */ + .macro save_and_disable_irqs, olddaif + mrs \olddaif, daif + disable_irq + .endm + + .macro restore_irqs, olddaif + msr daif, \olddaif + .endm + +/* + * __flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: x0-x7, x9-x11 + */ + .globl __flush_dcache_all +__flush_dcache_all: + dmb sy // ensure ordering with previous memory accesses + mrs x0, clidr_el1 // read clidr + and x3, x0, #0x7000000 // extract loc from clidr + lsr x3, x3, #23 // left align loc bit field + cbz x3, finished // if loc is 0, then no need to clean + mov x10, #0 // start clean at cache level 0 +loop1: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask of the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt skip // skip if no cache, or just i-cache + save_and_disable_irqs x9 // make CSSELR and CCSIDR access atomic + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + restore_irqs x9 + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + mov x4, #0x3ff + and x4, x4, x1, lsr #3 // find maximum number on the way size + clz w5, w4 // find bit position of way size increment + mov x7, #0x7fff + and x7, x7, x1, lsr #13 // extract max number of the index size +loop2: + mov x9, x4 // create working copy of max way size +loop3: + lsl x6, x9, x5 + orr x11, x10, x6 // factor way and cache number into x11 + lsl x6, x7, x2 + orr x11, x11, x6 // factor index number into x11 + dc cisw, x11 // clean & invalidate by set/way + subs x9, x9, #1 // decrement the way + b.ge loop3 + subs x7, x7, #1 // decrement the index + b.ge loop2 +skip: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.gt loop1 +finished: + mov x10, #0 // swith back to cache level 0 + msr csselr_el1, x10 // select current cache level in csselr + dsb sy + isb + ret +ENDPROC(__flush_dcache_all)