From patchwork Thu Jul 10 18:13:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 33447 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f200.google.com (mail-pd0-f200.google.com [209.85.192.200]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 8FAD6203C0 for ; Thu, 10 Jul 2014 18:15:54 +0000 (UTC) Received: by mail-pd0-f200.google.com with SMTP id v10sf57320904pde.7 for ; Thu, 10 Jul 2014 11:15:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=amLTb21e/Jx6LZ6p0vPxXDOdsAJGWVetaTEPq77iJ8Q=; b=iMphstNM56RwXwXn3UbrRTbR8dxOJMLYJK41dGqk8s9Hy7u2Vq45TBpmIWjEQsNIBy c3dBWMtLGOS3PqkZhZzAt+CF5kl7wyD17+0Br2JYyUjXvfZ/sw4Rw/at2GnZz7ZNOjwL dEow5BMAOoQ/000Oe9V4pMxusCI5ZkhBLDKF+/NcEXj6qz/MTQdHDFPRPdNXNXrw0SqL bnqdYIu1XPx9COEZrSdb+R4KKqWOTXr60cEOlX4M/SesmM5rsvf+u+w7cuvjwKmKJVFL kC/P4iRfRPi2L84mWCtbLhCyOBth4rcga3/hmECVzy9zK04QMsy6HDtmJBeaYkqupSZU aicw== X-Gm-Message-State: ALoCoQmeuNJ18glyqH4dO9AHbqOV8niF3n01JKCMnU5pGrw0k9WwPYi2/Jy+ZBEsdIYtj/PDWswf X-Received: by 10.66.151.140 with SMTP id uq12mr23913224pab.23.1405016153795; Thu, 10 Jul 2014 11:15:53 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.21.145 with SMTP id 17ls141088qgl.95.gmail; Thu, 10 Jul 2014 11:15:53 -0700 (PDT) X-Received: by 10.58.56.102 with SMTP id z6mr45925144vep.7.1405016153644; Thu, 10 Jul 2014 11:15:53 -0700 (PDT) Received: from mail-vc0-f174.google.com (mail-vc0-f174.google.com [209.85.220.174]) by mx.google.com with ESMTPS id xa4si23381747vcb.12.2014.07.10.11.15.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 10 Jul 2014 11:15:53 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) client-ip=209.85.220.174; Received: by mail-vc0-f174.google.com with SMTP id hy4so11376659vcb.33 for ; Thu, 10 Jul 2014 11:15:53 -0700 (PDT) X-Received: by 10.58.112.65 with SMTP id io1mr1792988veb.61.1405016153566; Thu, 10 Jul 2014 11:15:53 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp156627vcb; Thu, 10 Jul 2014 11:15:53 -0700 (PDT) X-Received: by 10.42.214.207 with SMTP id hb15mr56090770icb.30.1405016152713; Thu, 10 Jul 2014 11:15:52 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id c17si393320ici.87.2014.07.10.11.15.52 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 10 Jul 2014 11:15:52 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X5Irb-0008UF-Od; Thu, 10 Jul 2014 18:14:35 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X5IrX-0008PG-GD for xen-devel@lists.xensource.com; Thu, 10 Jul 2014 18:14:31 +0000 Received: from [85.158.143.35:41779] by server-2.bemta-4.messagelabs.com id DE/8F-18579-608DEB35; Thu, 10 Jul 2014 18:14:30 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-12.tower-21.messagelabs.com!1405016067!17166242!2 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 16534 invoked from network); 10 Jul 2014 18:14:29 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-12.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 10 Jul 2014 18:14:29 -0000 X-IronPort-AV: E=Sophos;i="5.01,639,1400025600"; d="scan'208";a="151781401" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 10 Jul 2014 18:14:25 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Thu, 10 Jul 2014 14:14:24 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1X5IrK-00037s-Vk; Thu, 10 Jul 2014 19:14:19 +0100 From: Stefano Stabellini To: Date: Thu, 10 Jul 2014 19:13:21 +0100 Message-ID: <1405016003-19131-8-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v8 08/10] xen/arm: take the rank lock before accessing ipriority X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Currently we read ipriority from vgic_vcpu_inject_irq without taking the rank lock. Fix that by taking the rank lock and reading ipriority at the beginning of the function. As vgic_vcpu_inject_irq is called from the irq.c upon receiving an interrupt, we need to change the implementation of vgic_lock/unlock_rank to spin_lock_irqsave to make it safe in irq context. Signed-off-by: Stefano Stabellini --- Changes in v2: - rebased on ab78724fc5628318b172b4344f7280621a151e1b; - remove warning on changing priority of active irqs. --- xen/arch/arm/vgic-v2.c | 2 ++ xen/arch/arm/vgic.c | 6 +++++- xen/include/asm-arm/vgic.h | 4 ++-- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 5116a99..ae31dbf 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -39,6 +39,7 @@ static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info) register_t *r = select_user_reg(regs, dabt.reg); struct vgic_irq_rank *rank; int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase); + unsigned long flags; switch ( gicd_reg ) { @@ -269,6 +270,7 @@ static int vgic_v2_distr_mmio_write(struct vcpu *v, mmio_info_t *info) struct vgic_irq_rank *rank; int gicd_reg = (int)(info->gpa - v->domain->arch.vgic.dbase); uint32_t tr; + unsigned long flags; switch ( gicd_reg ) { diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 569a859..fc51e87 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -175,6 +175,7 @@ struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int irq) { struct vcpu *v_target; struct vgic_irq_rank *rank = vgic_rank_irq(v, irq); + unsigned long flags; vgic_lock_rank(v, rank); v_target = _vgic_get_target_vcpu(v, irq); @@ -386,6 +387,10 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) bool_t running; struct vcpu *vcpu_migrate_from; + vgic_lock_rank(v, rank); + priority = vgic_byte_read(rank->ipriority[REG_RANK_INDEX(8, irq, DABT_WORD)], 0, irq & 0x3); + vgic_unlock_rank(v, rank); + spin_lock_irqsave(&v->arch.vgic.lock, flags); /* vcpu offline */ @@ -418,7 +423,6 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) goto out; } - priority = vgic_byte_read(rank->ipriority[REG_RANK_INDEX(8, irq, DABT_WORD)], 0, irq & 0x3); n->irq = irq; n->priority = priority; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index e961780..5d6a8ad 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -106,8 +106,8 @@ struct vgic_ops { #define vgic_lock(v) spin_lock_irq(&(v)->domain->arch.vgic.lock) #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock) -#define vgic_lock_rank(v, r) spin_lock(&(r)->lock) -#define vgic_unlock_rank(v, r) spin_unlock(&(r)->lock) +#define vgic_lock_rank(v, r) spin_lock_irqsave(&(r)->lock, flags) +#define vgic_unlock_rank(v, r) spin_unlock_irqrestore(&(r)->lock, flags) /* * Rank containing GICD_ for GICD_ with