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[50.57.142.19]) by mx.google.com with ESMTPS id x10si14445053igg.53.2014.07.10.11.16.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 10 Jul 2014 11:16:28 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X5IrY-0008Q5-Am; Thu, 10 Jul 2014 18:14:32 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X5IrV-0008OI-Gr for xen-devel@lists.xensource.com; Thu, 10 Jul 2014 18:14:29 +0000 Received: from [85.158.139.211:62870] by server-17.bemta-5.messagelabs.com id E1/E8-08711-408DEB35; Thu, 10 Jul 2014 18:14:28 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-12.tower-206.messagelabs.com!1405016065!14834761!2 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 27586 invoked from network); 10 Jul 2014 18:14:28 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-12.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 10 Jul 2014 18:14:28 -0000 X-IronPort-AV: E=Sophos;i="5.01,639,1400025600"; d="scan'208";a="151781394" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 10 Jul 2014 18:14:25 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Thu, 10 Jul 2014 14:14:24 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1X5IrK-00037s-VI; Thu, 10 Jul 2014 19:14:18 +0100 From: Stefano Stabellini To: Date: Thu, 10 Jul 2014 19:13:20 +0100 Message-ID: <1405016003-19131-7-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v8 07/10] xen/arm: remove workaround to inject evtchn_irq on irq enable X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: evtchn_upcall_pending is already set by common code at vcpu creation, therefore on ARM we also need to call vgic_vcpu_inject_irq for it. Currently we do that from vgic_enable_irqs as a workaround. Do this properly by calling vgic_vcpu_inject_irq in the appropriate places at vcpu creation time, making sure to call it after the vcpu is up (_VPF_down has been cleared). Return an error if arch_set_info_guest is called without VGCF_online set: at the moment no callers do that but if they did we would fail to inject the first evtchn_irq interrupt. Signed-off-by: Stefano Stabellini --- Changes in v2: - coding style fix; - add comment; - return an error if arch_set_info_guest is called without VGCF_online. --- xen/arch/arm/domain.c | 11 +++++++++-- xen/arch/arm/domain_build.c | 3 +++ xen/arch/arm/vgic.c | 18 ++++-------------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 87902ef..4417a90 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -659,6 +659,9 @@ int arch_set_info_guest( return -EINVAL; } #endif + /* we do not support calls to this functions without VGCF_online set */ + if ( !(ctxt->flags & VGCF_online) ) + return -EINVAL; vcpu_regs_user_to_hyp(v, regs); @@ -670,9 +673,13 @@ int arch_set_info_guest( v->is_initialised = 1; if ( ctxt->flags & VGCF_online ) + { clear_bit(_VPF_down, &v->pause_flags); - else - set_bit(_VPF_down, &v->pause_flags); + /* evtchn_upcall_pending is set by common code at vcpu creation, + * therefore on ARM we also need to call vgic_vcpu_inject_irq + * for it */ + vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); + } return 0; } diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 69188a4..ed43a4c 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -18,6 +18,7 @@ #include #include +#include #include #include "kernel.h" @@ -1378,6 +1379,8 @@ int construct_dom0(struct domain *d) } #endif + vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); + for ( i = 1, cpu = 0; i < d->max_vcpus; i++ ) { cpu = cpumask_cycle(cpu, &cpu_online_map); diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 704eaaf..569a859 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -281,20 +281,10 @@ void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) v_target = _vgic_get_target_vcpu(v, irq); p = irq_to_pending(v_target, irq); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status); - /* We need to force the first injection of evtchn_irq because - * evtchn_upcall_pending is already set by common code on vcpu - * creation. */ - if ( irq == v_target->domain->arch.evtchn_irq && - vcpu_info(current, evtchn_upcall_pending) && - list_empty(&p->inflight) ) - vgic_vcpu_inject_irq(v_target, irq); - else { - unsigned long flags; - spin_lock_irqsave(&v_target->arch.vgic.lock, flags); - if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) - gic_raise_guest_irq(v_target, irq, p->priority); - spin_unlock_irqrestore(&v_target->arch.vgic.lock, flags); - } + spin_lock_irqsave(&v_target->arch.vgic.lock, flags); + if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_raise_guest_irq(v_target, irq, p->priority); + spin_unlock_irqrestore(&v_target->arch.vgic.lock, flags); if ( p->desc != NULL ) { irq_set_affinity(p->desc, cpumask_of(v_target->processor));