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[50.57.142.19]) by mx.google.com with ESMTPS id g50si26973519qgg.23.2014.06.10.07.09.14 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 10 Jun 2014 07:09:15 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WuMiN-0000N6-Hp; Tue, 10 Jun 2014 14:07:51 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WuMiM-0000Mr-SU for xen-devel@lists.xensource.com; Tue, 10 Jun 2014 14:07:50 +0000 Received: from [85.158.139.211:59213] by server-1.bemta-5.messagelabs.com id BD/54-01663-63117935; Tue, 10 Jun 2014 14:07:50 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-11.tower-206.messagelabs.com!1402409266!5029227!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 24755 invoked from network); 10 Jun 2014 14:07:49 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-11.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 10 Jun 2014 14:07:49 -0000 X-IronPort-AV: E=Sophos; i="4.98,1009,1392163200"; d="scan'208"; a="141612263" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 10 Jun 2014 14:07:45 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.3.181.6; Tue, 10 Jun 2014 10:07:43 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WuMiA-0006am-PX; Tue, 10 Jun 2014 15:07:38 +0100 From: Stefano Stabellini To: Date: Tue, 10 Jun 2014 15:07:11 +0100 Message-ID: <1402409240-28114-3-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v9 03/12] xen/arm: set GICH_HCR_UIE if all the LRs are in use X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On return to guest, if there are no free LRs and we still have more interrupt to inject, set GICH_HCR_UIE so that we are going to receive a maintenance interrupt when no pending interrupts are present in the LR registers. The maintenance interrupt handler won't do anything anymore, but receiving the interrupt is going to cause gic_inject to be called on return to guest that is going to clear the old LRs and inject new interrupts. Signed-off-by: Stefano Stabellini Acked-by: Julien Grall Acked-by: Ian Campbell --- Changes in v5: - introduce lr_all_full() helper. Changes in v2: - disable/enable the GICH_HCR_UIE bit in GICH_HCR; - only enable GICH_HCR_UIE if this_cpu(lr_mask) == ((1 << nr_lrs) - 1). --- xen/arch/arm/gic.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 6d917a0..6b21945 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -55,6 +55,7 @@ static struct { static DEFINE_PER_CPU(uint64_t, lr_mask); static unsigned nr_lrs; +#define lr_all_full() (this_cpu(lr_mask) == ((1 << nr_lrs) - 1)) /* The GIC mapping of CPU interfaces does not necessarily match the * logical CPU numbering. Let's use mapping as returned by the GIC @@ -655,6 +656,13 @@ void gic_inject(void) vgic_vcpu_inject_irq(current, current->domain->arch.evtchn_irq); gic_restore_pending_irqs(current); + + + if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) + GICH[GICH_HCR] |= GICH_HCR_UIE; + else + GICH[GICH_HCR] &= ~GICH_HCR_UIE; + } static void do_sgi(struct cpu_user_regs *regs, int othercpu, enum gic_sgi sgi)