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[50.57.142.19]) by mx.google.com with ESMTPS id 69si26950244qgp.59.2014.06.10.07.09.54 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 10 Jun 2014 07:09:55 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WuMiU-0000Rc-8N; Tue, 10 Jun 2014 14:07:58 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WuMiT-0000QZ-9c for xen-devel@lists.xensource.com; Tue, 10 Jun 2014 14:07:57 +0000 Received: from [85.158.139.211:25722] by server-9.bemta-5.messagelabs.com id 66/22-04350-C3117935; Tue, 10 Jun 2014 14:07:56 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-15.tower-206.messagelabs.com!1402409268!5797672!3 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 32086 invoked from network); 10 Jun 2014 14:07:54 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-15.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 10 Jun 2014 14:07:54 -0000 X-IronPort-AV: E=Sophos; i="4.98,1009,1392163200"; d="scan'208"; a="141612291" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 10 Jun 2014 14:07:49 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.3.181.6; Tue, 10 Jun 2014 10:07:44 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WuMiA-0006am-VT; Tue, 10 Jun 2014 15:07:39 +0100 From: Stefano Stabellini To: Date: Tue, 10 Jun 2014 15:07:18 +0100 Message-ID: <1402409240-28114-10-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v9 10/12] xen/arm: don't protect GICH and lr_queue accesses with gic.lock X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: GICH is banked, protect accesses by disabling interrupts. Protect lr_queue accesses with the vgic.lock only. gic.lock only protects accesses to GICD now. Signed-off-by: Stefano Stabellini Acked-by: Ian Campbell Acked-by: Julien Grall --- Changes in v5: - gic_remove_from_queues need to be protected with a vgic lock; - introduce ASSERTs to check the vgic is locked and interrupts are disabled. Changes in v4: - improved in code comments. --- xen/arch/arm/gic.c | 32 +++++++++++++++++--------------- xen/arch/arm/vgic.c | 9 +++++++-- xen/include/asm-arm/domain.h | 5 ++++- 3 files changed, 28 insertions(+), 18 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 4fb5c01..29c0502 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -113,6 +113,7 @@ void gic_save_state(struct vcpu *v) void gic_restore_state(struct vcpu *v) { int i; + ASSERT(!local_irq_is_enabled()); if ( is_idle_vcpu(v) ) return; @@ -549,6 +550,7 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, { uint32_t lr_val; + ASSERT(!local_irq_is_enabled()); BUG_ON(lr >= nr_lrs); BUG_ON(lr < 0); BUG_ON(state & ~(GICH_LR_STATE_MASK<arch.vgic.lock)); + if ( !list_empty(&n->lr_queue) ) return; @@ -588,16 +592,18 @@ void gic_remove_from_queues(struct vcpu *v, unsigned int virtual_irq) struct pending_irq *p = irq_to_pending(v, virtual_irq); unsigned long flags; - spin_lock_irqsave(&gic.lock, flags); + spin_lock_irqsave(&v->arch.vgic.lock, flags); if ( !list_empty(&p->lr_queue) ) list_del_init(&p->lr_queue); - spin_unlock_irqrestore(&gic.lock, flags); + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); } void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) { struct pending_irq *n = irq_to_pending(v, virtual_irq); + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + if ( list_empty(&n->lr_queue) ) { if ( v == current ) @@ -614,9 +620,8 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, unsigned int priority) { int i; - unsigned long flags; - spin_lock_irqsave(&gic.lock, flags); + ASSERT(spin_is_locked(&v->arch.vgic.lock)); if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) { @@ -624,15 +629,11 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, if (i < nr_lrs) { set_bit(i, &this_cpu(lr_mask)); gic_set_lr(i, irq_to_pending(v, virtual_irq), GICH_LR_PENDING); - goto out; + return; } } gic_add_to_lr_pending(v, irq_to_pending(v, virtual_irq)); - -out: - spin_unlock_irqrestore(&gic.lock, flags); - return; } static void gic_update_one_lr(struct vcpu *v, int i) @@ -642,6 +643,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) int irq; ASSERT(spin_is_locked(&v->arch.vgic.lock)); + ASSERT(!local_irq_is_enabled()); lr = GICH[GICH_LR + i]; irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK; @@ -708,30 +710,28 @@ static void gic_restore_pending_irqs(struct vcpu *v) struct pending_irq *p, *t; unsigned long flags; + spin_lock_irqsave(&v->arch.vgic.lock, flags); list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) { i = find_first_zero_bit(&this_cpu(lr_mask), nr_lrs); if ( i >= nr_lrs ) return; - spin_lock_irqsave(&gic.lock, flags); gic_set_lr(i, p, GICH_LR_PENDING); list_del_init(&p->lr_queue); set_bit(i, &this_cpu(lr_mask)); - spin_unlock_irqrestore(&gic.lock, flags); } - + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); } void gic_clear_pending_irqs(struct vcpu *v) { struct pending_irq *p, *t; - unsigned long flags; - spin_lock_irqsave(&gic.lock, flags); + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + v->arch.lr_mask = 0; list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) list_del_init(&p->lr_queue); - spin_unlock_irqrestore(&gic.lock, flags); } int gic_events_need_delivery(void) @@ -742,6 +742,8 @@ int gic_events_need_delivery(void) void gic_inject(void) { + ASSERT(!local_irq_is_enabled()); + gic_restore_pending_irqs(current); diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index c7abf9f..cb8df3a 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -411,8 +411,13 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) vcpu_info(current, evtchn_upcall_pending) && list_empty(&p->inflight) ) vgic_vcpu_inject_irq(v, irq); - else if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) - gic_raise_guest_irq(v, irq, p->priority); + else { + unsigned long flags; + spin_lock_irqsave(&v->arch.vgic.lock, flags); + if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_raise_guest_irq(v, irq, p->priority); + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + } if ( p->desc != NULL ) { spin_lock_irqsave(&p->desc->lock, flags); diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index c39756f..59ce196 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -68,7 +68,10 @@ struct pending_irq * vgic.inflight_irqs */ struct list_head inflight; /* lr_queue is used to append instances of pending_irq to - * gic.lr_pending */ + * lr_pending. lr_pending is a per vcpu queue, therefore lr_queue + * accesses are protected with the vgic lock. + * TODO: when implementing irq migration, taking only the current + * vgic lock is not going to be enough. */ struct list_head lr_queue; };