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[50.57.142.19]) by mx.google.com with ESMTPS id db7si18694508wjb.99.2014.06.06.10.50.12 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 06 Jun 2014 10:50:13 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WsyG7-0000ka-Nq; Fri, 06 Jun 2014 17:48:55 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WsyG5-0000jR-Lb for xen-devel@lists.xensource.com; Fri, 06 Jun 2014 17:48:53 +0000 Received: from [85.158.143.35:5471] by server-2.bemta-4.messagelabs.com id F3/3A-06539-40FF1935; Fri, 06 Jun 2014 17:48:52 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-6.tower-21.messagelabs.com!1402076930!9724858!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23064 invoked from network); 6 Jun 2014 17:48:52 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-6.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 6 Jun 2014 17:48:52 -0000 X-IronPort-AV: E=Sophos;i="4.98,990,1392163200"; d="scan'208";a="140457354" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 06 Jun 2014 17:48:48 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.3.181.6; Fri, 6 Jun 2014 13:48:47 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WsyFu-00015p-OP; Fri, 06 Jun 2014 18:48:42 +0100 From: Stefano Stabellini To: Date: Fri, 6 Jun 2014 18:48:28 +0100 Message-ID: <1402076908-26740-4-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, JBeulich@suse.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v4 4/4] xen/arm: physical irq follow virtual irq X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Migrate physical irqs to the same physical cpu that is running the vcpu expected to receive the irqs. That is done when enabling irqs, when the guest writes to GICD_ITARGETSR and when Xen migrates a vcpu to a different pcpu. Introduce a new hook in common code to call the vgic irq migration code as evtchn_move_pirqs only deals with event channels at the moment. Signed-off-by: Stefano Stabellini CC: JBeulich@suse.com --- xen/arch/arm/gic.c | 18 ++++++++++++++++-- xen/arch/arm/vgic.c | 31 +++++++++++++++++++++++++++++++ xen/common/event_channel.c | 4 ++++ xen/include/asm-arm/gic.h | 1 + 4 files changed, 52 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 6f24b14..43bef21 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -192,9 +192,23 @@ static void gic_guest_irq_end(struct irq_desc *desc) /* Deactivation happens in maintenance interrupt / via GICV */ } -static void gic_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask) +static void gic_irq_set_affinity(struct irq_desc *desc, const cpumask_t *cpu_mask) { - BUG(); + volatile unsigned char *bytereg; + unsigned int mask; + + if ( desc == NULL || cpumask_empty(cpu_mask) ) + return; + + spin_lock(&gic.lock); + + mask = gic_cpu_mask(cpu_mask); + + /* Set target CPU mask (RAZ/WI on uniprocessor) */ + bytereg = (unsigned char *) (GICD + GICD_ITARGETSR); + bytereg[desc->irq] = mask; + + spin_unlock(&gic.lock); } /* XXX different for level vs edge */ diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 54d3676..a90d9cb 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -408,6 +408,32 @@ struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int irq) return v_target; } +void vgic_move_irqs(struct vcpu *v) +{ + const cpumask_t *cpu_mask = cpumask_of(v->processor); + struct domain *d = v->domain; + struct pending_irq *p; + int i, j, k; + + for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ ) + { + for ( j = 0 ; j < 8 ; j++ ) + { + for ( k = 0; k < 4; k++ ) + { + uint8_t target = byte_read(d->arch.vgic.shared_irqs[i].itargets[j], 0, k); + target = find_next_bit((const unsigned long *) &target, 8, 0); + if ( target == v->vcpu_id ) + { + p = irq_to_pending(v, 32 * (i + 1) + (j * 4) + k); + if ( p->desc != NULL ) + p->desc->handler->set_affinity(p->desc, cpu_mask); + } + } + } + } +} + static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) { const unsigned long mask = r; @@ -463,6 +489,7 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) } if ( p->desc != NULL ) { + p->desc->handler->set_affinity(p->desc, cpumask_of(v_target->processor)); spin_lock_irqsave(&p->desc->lock, flags); p->desc->handler->enable(p->desc); spin_unlock_irqrestore(&p->desc->lock, flags); @@ -649,6 +676,7 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info) { unsigned int irq, target, old_target; struct vcpu *v_target, *v_old; + struct pending_irq *p; target = i % 8; @@ -657,6 +685,9 @@ static int vgic_distr_mmio_write(struct vcpu *v, mmio_info_t *info) old_target = byte_read(rank->itargets[REG_RANK_INDEX(8, gicd_reg - GICD_ITARGETSR)], 0, i/8); v_old = v->domain->vcpu[old_target]; vgic_migrate_irq(v_old, v_target, irq); + p = irq_to_pending(v_target, irq); + if ( p->desc != NULL ) + p->desc->handler->set_affinity(p->desc, cpumask_of(v_target->processor)); i += 8 - target; } if ( dabt.size == 2 ) diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c index 6853842..226321d 100644 --- a/xen/common/event_channel.c +++ b/xen/common/event_channel.c @@ -1319,6 +1319,10 @@ void evtchn_move_pirqs(struct vcpu *v) unsigned int port; struct evtchn *chn; +#ifdef CONFIG_ARM + vgic_move_irqs(v); +#endif + spin_lock(&d->event_lock); for ( port = v->pirq_evtchn_head; port; port = chn->u.pirq.next_port ) { diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index bd40628..8f457dd 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -228,6 +228,7 @@ int gic_irq_xlate(const u32 *intspec, unsigned int intsize, void gic_clear_lrs(struct vcpu *v); struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int irq); +void vgic_move_irqs(struct vcpu *v); #endif /* __ASSEMBLY__ */ #endif