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[50.57.142.19]) by mx.google.com with ESMTPS id fv10si3036168vdc.39.2014.05.22.05.34.13 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 22 May 2014 05:34:14 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WnSBU-0004LO-V8; Thu, 22 May 2014 12:33:20 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WnSBS-0004IQ-L0 for xen-devel@lists.xensource.com; Thu, 22 May 2014 12:33:18 +0000 Received: from [193.109.254.147:46562] by server-16.bemta-14.messagelabs.com id 73/99-16986-D8EED735; Thu, 22 May 2014 12:33:17 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-10.tower-27.messagelabs.com!1400761994!6480922!3 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 26610 invoked from network); 22 May 2014 12:33:17 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-10.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 22 May 2014 12:33:17 -0000 X-IronPort-AV: E=Sophos;i="4.98,887,1392163200"; d="scan'208";a="133886191" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 22 May 2014 12:33:15 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.3.181.6; Thu, 22 May 2014 08:33:13 -0400 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WnSBI-0003tn-9g; Thu, 22 May 2014 13:33:08 +0100 From: Stefano Stabellini To: Date: Thu, 22 May 2014 13:32:25 +0100 Message-ID: <1400761950-25035-8-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH v8 08/13] xen/arm: rename GIC_IRQ_GUEST_PENDING to GIC_IRQ_GUEST_QUEUED X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Rename GIC_IRQ_GUEST_PENDING to GIC_IRQ_GUEST_QUEUED and clarify its meaning in xen/include/asm-arm/domain.h. Signed-off-by: Stefano Stabellini Acked-by: Julien Grall Acked-by: Ian Campbell --- Changes in v8: - update comment in domain.h to better reflect the renaming. --- xen/arch/arm/gic.c | 4 ++-- xen/arch/arm/vgic.c | 4 ++-- xen/include/asm-arm/domain.h | 23 ++++++++++++----------- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 2a2f63e..89d7025 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -559,7 +559,7 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, GICH[GICH_LR + lr] = lr_val; set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - clear_bit(GIC_IRQ_GUEST_PENDING, &p->status); + clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); p->lr = lr; } @@ -637,7 +637,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) p->desc->status &= ~IRQ_INPROGRESS; clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); p->lr = GIC_INVALID_LR; - if ( test_bit(GIC_IRQ_GUEST_PENDING, &p->status) && + if ( test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && test_bit(GIC_IRQ_GUEST_ENABLED, &p->status)) gic_raise_guest_irq(v, irq, p->priority); else diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index b6c3ebe..b44937d 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -719,7 +719,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) { if ( (irq != current->domain->arch.evtchn_irq) || (!test_bit(GIC_IRQ_GUEST_VISIBLE, &n->status)) ) - set_bit(GIC_IRQ_GUEST_PENDING, &n->status); + set_bit(GIC_IRQ_GUEST_QUEUED, &n->status); goto out; } @@ -733,7 +733,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) priority = byte_read(rank->ipriority[REG_RANK_INDEX(8, idx)], 0, byte); n->irq = irq; - set_bit(GIC_IRQ_GUEST_PENDING, &n->status); + set_bit(GIC_IRQ_GUEST_QUEUED, &n->status); n->priority = priority; /* the irq is enabled */ diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index e5db9e3..c39756f 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -27,7 +27,8 @@ struct pending_irq * whether an irq added to an LR register is PENDING or ACTIVE, the * following states are just an approximation. * - * GIC_IRQ_GUEST_PENDING: the irq is asserted + * GIC_IRQ_GUEST_QUEUED: the irq is asserted and queued for + * injection into the guest's LRs. * * GIC_IRQ_GUEST_VISIBLE: the irq has been added to an LR register, * therefore the guest is aware of it. From the guest point of view @@ -35,16 +36,16 @@ struct pending_irq * or active (after acking the irq). * * In order for the state machine to be fully accurate, for level - * interrupts, we should keep the GIC_IRQ_GUEST_PENDING state until + * interrupts, we should keep the interrupt's pending state until * the guest deactivates the irq. However because we are not sure - * when that happens, we simply remove the GIC_IRQ_GUEST_PENDING - * state when we add the irq to an LR register. We add it back when - * we receive another interrupt notification. - * Therefore it is possible to set GIC_IRQ_GUEST_PENDING while the - * irq is GIC_IRQ_GUEST_VISIBLE. We could also change the state of - * the guest irq in the LR register from active to active and - * pending, but for simplicity we simply inject a second irq after - * the guest EOIs the first one. + * when that happens, we instead track whether there is an interrupt + * queued using GIC_IRQ_GUEST_QUEUED. We clear it when we add it to + * an LR register. We set it when we receive another interrupt + * notification. Therefore it is possible to set + * GIC_IRQ_GUEST_QUEUED while the irq is GIC_IRQ_GUEST_VISIBLE. We + * could also change the state of the guest irq in the LR register + * from active to active and pending, but for simplicity we simply + * inject a second irq after the guest EOIs the first one. * * * An additional state is used to keep track of whether the guest @@ -54,7 +55,7 @@ struct pending_irq * level (GICD_ICENABLER/GICD_ISENABLER). * */ -#define GIC_IRQ_GUEST_PENDING 0 +#define GIC_IRQ_GUEST_QUEUED 0 #define GIC_IRQ_GUEST_VISIBLE 1 #define GIC_IRQ_GUEST_ENABLED 2 unsigned long status;