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[50.57.142.19]) by mx.google.com with ESMTPS id ub5si2716727vcb.147.2014.05.13.08.51.53 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 13 May 2014 08:51:53 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WkEyV-0008Iz-0W; Tue, 13 May 2014 15:50:39 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WkEyT-0008Id-9a for xen-devel@lists.xenproject.org; Tue, 13 May 2014 15:50:37 +0000 Received: from [193.109.254.147:30956] by server-15.bemta-14.messagelabs.com id E4/E9-15813-C4F32735; Tue, 13 May 2014 15:50:36 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-8.tower-27.messagelabs.com!1399996235!4565400!1 X-Originating-IP: [74.125.83.42] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 19108 invoked from network); 13 May 2014 15:50:36 -0000 Received: from mail-ee0-f42.google.com (HELO mail-ee0-f42.google.com) (74.125.83.42) by server-8.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 13 May 2014 15:50:36 -0000 Received: by mail-ee0-f42.google.com with SMTP id d49so562792eek.1 for ; Tue, 13 May 2014 08:50:35 -0700 (PDT) X-Received: by 10.14.98.131 with SMTP id v3mr4891875eef.77.1399996235705; Tue, 13 May 2014 08:50:35 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id m44sm41054917eeh.14.2014.05.13.08.50.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 May 2014 08:50:35 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 13 May 2014 16:50:17 +0100 Message-Id: <1399996230-18201-2-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1399996230-18201-1-git-send-email-julien.grall@linaro.org> References: <1399996230-18201-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v5 01/14] xen/arm: Introduce flush_tlb_domain X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The pattern p2m_load_VTTBR(d) -> flush_tlb -> p2m_load_VTTBR(current->domain) is used in few places. Replace this usage by flush_tlb_domain which will take care of this pattern. This will help to the lisibility of apply_p2m_changes which begin to be big. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v5: - Patch added --- xen/arch/arm/p2m.c | 35 +++++++++++++++++------------------ xen/include/asm-arm/flushtlb.h | 3 +++ 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 603c097..61450cf 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -72,6 +72,21 @@ void p2m_restore_state(struct vcpu *n) isb(); } +void flush_tlb_domain(struct domain *d) +{ + /* Update the VTTBR if necessary with the domain d. In this case, + * it's only necessary to flush TLBs on every CPUs with the current VMID + * (our domain). + */ + if ( d != current->domain ) + p2m_load_VTTBR(d); + + flush_tlb(); + + if ( d != current->domain ) + p2m_load_VTTBR(current->domain); +} + static int p2m_first_level_index(paddr_t addr) { /* @@ -450,19 +465,7 @@ static int apply_p2m_changes(struct domain *d, } if ( flush ) - { - /* Update the VTTBR if necessary with the domain where mappings - * are created. In this case it's only necessary to flush TLBs - * on every CPUs with the current VMID (our domain). - */ - if ( d != current->domain ) - p2m_load_VTTBR(d); - - flush_tlb(); - - if ( d != current->domain ) - p2m_load_VTTBR(current->domain); - } + flush_tlb_domain(d); if ( op == ALLOCATE || op == INSERT ) { @@ -550,14 +553,10 @@ int p2m_alloc_table(struct domain *d) d->arch.vttbr = page_to_maddr(p2m->first_level) | ((uint64_t)p2m->vmid&0xff)<<48; - p2m_load_VTTBR(d); - /* Make sure that all TLBs corresponding to the new VMID are flushed * before using it */ - flush_tlb(); - - p2m_load_VTTBR(current->domain); + flush_tlb_domain(d); spin_unlock(&p2m->lock); diff --git a/xen/include/asm-arm/flushtlb.h b/xen/include/asm-arm/flushtlb.h index 329fbb4..5722c67 100644 --- a/xen/include/asm-arm/flushtlb.h +++ b/xen/include/asm-arm/flushtlb.h @@ -25,6 +25,9 @@ do { \ /* Flush specified CPUs' TLBs */ void flush_tlb_mask(const cpumask_t *mask); +/* Flush CPU's TLBs for the speficied domain */ +void flush_tlb_domain(struct domain *d); + #endif /* __ASM_ARM_FLUSHTLB_H__ */ /* * Local variables: