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[50.57.142.19]) by mx.google.com with ESMTPS id ax8si1202963igc.18.2014.04.24.15.48.52 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 24 Apr 2014 15:49:11 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WdSPI-0003MD-BH; Thu, 24 Apr 2014 22:46:16 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WdSPG-0003M0-GD for xen-devel@lists.xenproject.org; Thu, 24 Apr 2014 22:46:14 +0000 Received: from [85.158.137.68:55134] by server-10.bemta-3.messagelabs.com id B6/49-16608-53499535; Thu, 24 Apr 2014 22:46:13 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-10.tower-31.messagelabs.com!1398379572!8856055!1 X-Originating-IP: [74.125.83.54] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 21397 invoked from network); 24 Apr 2014 22:46:12 -0000 Received: from mail-ee0-f54.google.com (HELO mail-ee0-f54.google.com) (74.125.83.54) by server-10.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 24 Apr 2014 22:46:12 -0000 Received: by mail-ee0-f54.google.com with SMTP id d49so2326842eek.27 for ; Thu, 24 Apr 2014 15:46:12 -0700 (PDT) X-Received: by 10.15.82.132 with SMTP id a4mr5056304eez.47.1398379572660; Thu, 24 Apr 2014 15:46:12 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id t44sm19683823eeo.6.2014.04.24.15.46.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Apr 2014 15:46:11 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 24 Apr 2014 23:45:56 +0100 Message-Id: <1398379556-1132-5-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1398379556-1132-1-git-send-email-julien.grall@linaro.org> References: <1398379556-1132-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH 4/4] xen/arm: Add some useful debug in coprocessor trapping X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: XSA-93 adds a couple of new functions to trap coprocessor registers. They unconditonally inject an undefined instruction to guest. When debugging an OS at early stage, it may be hard to know why the guest received an UNDEFINED. Add some debug message to help the developper when Xen is built in debug mode. Signed-off-by: Julien Grall --- xen/arch/arm/traps.c | 18 ++++++++++++++++++ xen/include/asm-arm/processor.h | 15 +++++++++++++-- 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1f61e6e..c04f53f 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1539,23 +1539,41 @@ bad_cp: static void do_cp14_dbg(struct cpu_user_regs *regs, union hsr hsr) { + struct hsr_cp64 cp64 = hsr.cp64; + if ( !check_conditional_instr(regs, hsr) ) { advance_pc(regs, hsr); return; } +#ifndef NDEBUG + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n", + cp64.read ? "mrrc" : "mcrr", + cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n", + hsr.bits & HSR_CP64_REGS_MASK); +#endif inject_undef32_exception(regs); } static void do_cp(struct cpu_user_regs *regs, union hsr hsr) { +#ifndef NDEBUG + struct hsr_cp cp = hsr.cp; +#endif + if ( !check_conditional_instr(regs, hsr) ) { advance_pc(regs, hsr); return; } +#ifndef NDEBUG + ASSERT(!cp.tas); /* We don't trap SIMD instruction */ + gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc); +#endif inject_undef32_exception(regs); } diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 9267c1b..bc29de1 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -289,12 +289,23 @@ union hsr { unsigned long reg2:5; /* Rt2 */ unsigned long sbzp2:1; unsigned long op1:4; /* Op1 */ - unsigned long cc:4; /* Condition Code */ - unsigned long ccvalid:1;/* CC Valid */ + unsigned long cc:4; /* condition code */ + unsigned long ccvalid:1;/* cc valid */ unsigned long len:1; /* Instruction length */ unsigned long ec:6; /* Exception Class */ } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */ + struct hsr_cp { + unsigned long coproc:4; /* Number of coproc accessed */ + unsigned long sbz0p:1; + unsigned long tas:1; /* Trapped Advanced SIMD */ + unsigned long res0:14; + unsigned long cc:4; /* condition code */ + unsigned long ccvalid:1;/* cc valid */ + unsigned long len:1; /* Instruction length */ + unsigned long ec:6; /* Exception Class */ + } cp; /* HSR_EC_CP */ + #ifdef CONFIG_ARM_64 struct hsr_sysreg { unsigned long read:1; /* Direction */