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[50.57.142.19]) by mx.google.com with ESMTPS id v6si2980588qas.45.2014.04.24.15.49.10 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 24 Apr 2014 15:49:10 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WdSPE-0003Lq-UU; Thu, 24 Apr 2014 22:46:12 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WdSPD-0003Lj-Fh for xen-devel@lists.xenproject.org; Thu, 24 Apr 2014 22:46:11 +0000 Received: from [85.158.139.211:41925] by server-16.bemta-5.messagelabs.com id A2/30-19700-23499535; Thu, 24 Apr 2014 22:46:10 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-7.tower-206.messagelabs.com!1398379569!489939!1 X-Originating-IP: [74.125.83.48] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 5130 invoked from network); 24 Apr 2014 22:46:09 -0000 Received: from mail-ee0-f48.google.com (HELO mail-ee0-f48.google.com) (74.125.83.48) by server-7.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 24 Apr 2014 22:46:09 -0000 Received: by mail-ee0-f48.google.com with SMTP id b57so2284344eek.21 for ; Thu, 24 Apr 2014 15:46:09 -0700 (PDT) X-Received: by 10.14.176.193 with SMTP id b41mr5054495eem.55.1398379569643; Thu, 24 Apr 2014 15:46:09 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id t44sm19683823eeo.6.2014.04.24.15.46.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 Apr 2014 15:46:08 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 24 Apr 2014 23:45:55 +0100 Message-Id: <1398379556-1132-4-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1398379556-1132-1-git-send-email-julien.grall@linaro.org> References: <1398379556-1132-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH 3/4] xen/arm: Implement a dummy debug monitor for ARM32 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: XSA-93 (commit 0b18220 "xen/arm: Don't let guess access to Debug and Performance Monitors registers") disable Debug Registers access. When CONFIG_PERF_EVENTS is enabled in the Linux Kernel, it will try to initialize the debug monitors. If an error occured Linux won't use this feature. The implementation made Xen expose a minimal set of registers which let think the guest (i.e.) thinks HW debug won't work. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- This commit is candidate for backporting on Xen 4.4. Distribution may enable HW DEBUG (e.g. Linaro Ubuntu image), therefore Linux will try to initialize it. --- xen/arch/arm/traps.c | 77 ++++++++++++++++++++++++++++++++++++++++-- xen/include/asm-arm/cpregs.h | 14 ++++++++ 2 files changed, 89 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 319bbe9..1f61e6e 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1468,7 +1468,76 @@ static void do_cp15_64(struct cpu_user_regs *regs, advance_pc(regs, hsr); } -static void do_cp14(struct cpu_user_regs *regs, union hsr hsr) +static void do_cp14_32(struct cpu_user_regs *regs, union hsr hsr) +{ + struct hsr_cp32 cp32 = hsr.cp32; + uint32_t *r = (uint32_t *)select_user_reg(regs, cp32.reg); + struct domain *d = current->domain; + + if ( !check_conditional_instr(regs, hsr) ) + { + advance_pc(regs, hsr); + return; + } + + switch ( hsr.bits & HSR_CP32_REGS_MASK ) + { + case HSR_CPREG32(DBGDIDR): + + /* Read-only register */ + if ( !cp32.read ) + goto bad_cp; + + /* Implement the minimum requirements: + * - Number of watchpoints: 1 + * - Number of breakpoints: 2 + * - Version: ARMv7 v7.1 + * - Variant and Revision bits match MDIR + */ + *r = (1 << 24) | (5 << 16); + *r |= ((d->arch.vpidr >> 20) & 0xf) | (d->arch.vpidr & 0xf); + break; + + case HSR_CPREG32(DBGDSCRINT): + case HSR_CPREG32(DBGDSCREXT): + /* Implement debug status and control register as RAZ/WI. + * The OS won't use Hardware debug if MDBGen not set + */ + if ( cp32.read ) + *r = 0; + break; + case HSR_CPREG32(DBGVCR): + case HSR_CPREG32(DBGOSLAR): + case HSR_CPREG32(DBGBVR0): + case HSR_CPREG32(DBGCR0): + case HSR_CPREG32(DBGWVR0): + case HSR_CPREG32(DBGWCR0): + case HSR_CPREG32(DBGBVR1): + case HSR_CPREG32(DBGCR1): + case HSR_CPREG32(DBGOSDLR): + /* RAZ/WI */ + if ( cp32.read ) + *r = 0; + break; + + default: +bad_cp: +#ifndef NDEBUG + gdprintk(XENLOG_ERR, + "%s p14, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n", + cp32.read ? "mrc" : "mcr", + cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc); + gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n", + hsr.bits & HSR_CP32_REGS_MASK); +#endif + inject_undef32_exception(regs); + return; + } + + advance_pc(regs, hsr); +} + +static void do_cp14_dbg(struct cpu_user_regs *regs, union hsr hsr) { if ( !check_conditional_instr(regs, hsr) ) { @@ -1720,10 +1789,14 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs *regs) do_cp15_64(regs, hsr); break; case HSR_EC_CP14_32: + if ( !is_32bit_domain(current->domain) ) + goto bad_trap; + do_cp14_32(regs, hsr); + break; case HSR_EC_CP14_DBG: if ( !is_32bit_domain(current->domain) ) goto bad_trap; - do_cp14(regs, hsr); + do_cp14_dbg(regs, hsr); break; case HSR_EC_CP: if ( !is_32bit_domain(current->domain) ) diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index f44e3b5..306e506 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -71,6 +71,20 @@ /* Coprocessor 14 */ +/* CP14 0: Debug Register interface */ +#define DBGDIDR p14,0,c0,c0,0 /* Debug ID Register */ +#define DBGDSCRINT p14,0,c0,c1,0 /* Debug Status and Control Internal */ +#define DBGDSCREXT p14,0,c0,c2,2 /* Debug Status and Control External */ +#define DBGVCR p14,0,c0,c7,0 /* Vector Catch */ +#define DBGBVR0 p14,0,c0,c0,4 /* Breakpoint Value 0 */ +#define DBGCR0 p14,0,c0,c0,5 /* Breakpoint Control 0 */ +#define DBGWVR0 p14,0,c0,c0,6 /* Watchpoint Value 0 */ +#define DBGWCR0 p14,0,c0,c0,7 /* Watchpoint Control 0 */ +#define DBGBVR1 p14,0,c0,c1,4 /* Breakpoint Value 1 */ +#define DBGCR1 p14,0,c0,c1,5 /* Breakpoint Control 1 */ +#define DBGOSLAR p14,0,c1,c0,4 /* OS Lock Access */ +#define DBGOSDLR p14,0,c1,c3,4 /* OS Double Lock */ + /* CP14 CR0: */ #define TEECR p14,6,c0,c0,0 /* ThumbEE Configuration Register */